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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 dac38rfxx: dual- or single-channel, single-ended, 14-bit, 9-gsps, rf-sampling dac with jesd204b interface and on-chip gsm pll 1 1 features 1 ? 14-bit resolution ? maximum dac sample rate: 9 gsps ? key specifications: ? rf full scale output power at 2.1 ghz: 0 dbm ? spectral performance ? f dac = 5898.24 msps, f out = 2.14 ghz ? wcdma aclr: 73 dbc ? wcdma alt-aclr: 77 dbc ? f dac = 8847.36 msps, f out = 3.7 ghz ? 20 mhz lte aclr: 66 dbc ? f dac = 9 gsps, f out = 1.8 ghz ? imd3 = 70 dbc ( ? 6 dbfs, 10 mhz tone spacing) ? nsd = ? 157 dbc/hz ? dual-band digital upconverter per dac ? max input rate: 1 band: 1250 msps complex, 2 bands: 625 msps complex each ? 6, 8, 10, 12, 16, 18, 20 or 24x interpolation ? 4 independent ncos with 48-bit resolution ? jesd204b interface ? subclass 1 support for multi-chip synchronization ? maximum lane rate: 12.5 gbps ? single-ended output with integrated balun covering 700 ? 3800 mhz ? internal pll and vco with bypass ? dac38rf86/96: f c(vco) = 8.9 ghz ? dac38rf87/97: f c(vco) = 5.9 ghz ? power dissipation: 1.4 ? 2.2 w/ch ? power supplies: ? 1.8 v, 1.0 v, 1.8 v ? package: 10 x 10 mm bga, 0.8 mm pitch, 144-balls 2 applications ? wireless communications ? radar ? communications test equipment ? arbitrary waveform generators ? military software defined radio ? satellite communications (satcom) 3 description the dac38rfxx is a family of high-performance, dual/single-channel, 14-bit, 9-gsps, rf-sampling digital-to-analog converters (dacs) that are capable of synthesizing wideband signals from 0 to 4.5 ghz. a high dynamic range allows the dac38rfxx family to generate 3g/4g signals for wireless basestations with an output frequency up to 4 ghz. the devices feature a low-power jesd204b interface with up to 8 lanes, and provides a maximum bit rate of 12.5 gbps and input sample rate of 1.25 gsps complex per channel. the dac38rfxx provides two digital upconverters per dac, with multiple interpolation rates and a digital quadrature modulator with independent, frequency flexible ncos. an optional low-jitter pll/vco simplifies the dac clock generation by allowing use of a lower frequency reference clock. device information (1) part number package body size (nom) dac38rf86 fcbga (144) 10.0 mm x 10.0 mm dac38rf96 dac38rf87 dac38rf97 (1) for all available packages, see the orderable addendum at the end of the data sheet. 2x20 mhz lte at 1.84 ghz and 2.14 ghz, 800 mhz span productfolder ordernow technical documents tools & software support &community
2 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 4 7 specifications ......................................................... 7 7.1 absolute maximum ratings ...................................... 7 7.2 esd ratings .............................................................. 7 7.3 recommended operating conditions ....................... 7 7.4 thermal information .................................................. 8 7.5 electrical characteristics - dc specifications ........... 8 7.6 electrical characteristics - digital specifications .... 11 7.7 electrical characteristics - ac specifications ......... 14 7.8 timing requirements .............................................. 17 7.9 typical characteristics ............................................ 18 8 detailed description ............................................ 23 8.1 overview ................................................................. 23 8.2 functional block diagrams ..................................... 23 8.3 feature description ................................................. 25 8.4 device functional modes ........................................ 59 8.5 register maps ........................................................ 62 9 application and implementation ...................... 125 9.1 application information .......................................... 125 9.2 typical application: multi-band radio frequency transmitter ............................................................ 126 10 power supply recommendations ................... 130 10.1 power supply sequencing .................................. 131 11 layout ................................................................. 132 11.1 layout guidelines ............................................... 132 11.2 layout example .................................................. 134 12 device and documentation support ............... 135 12.1 related links ...................................................... 135 12.2 receiving notification of documentation updates .................................................................. 135 12.3 community resources ........................................ 135 12.4 trademarks ......................................................... 135 12.5 electrostatic discharge caution .......................... 135 12.6 glossary .............................................................. 135 13 mechanical, packaging, and orderable information ......................................................... 135 4 revision history date revision notes february 2017 * initial release.
3 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 device comparison table device no. of channels output interpolation vco center frequency dac38rf86 2 single ended 6-24 vco0 = vco1 = 8.85 ghz dac38rf96 2 12-24 vco0 = vco1 = 8.85 ghz dac38rf87 2 6-24 vco0 = vco1 = 5.9 ghz dac38rf97 2 12-24 vco0 = vco1 = 5.9 ghz
4 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 6 pin configuration and functions aav package 144-pin (fcbga) 144-pin fcbga top view a b c d e f g h j k l m 12 dacclkse vssclk agnd agnd vout2 agnd vddout18 vddout18 agnd vout1 agnd agnd 12 11 vssclk vssclk agnd agnd agnd vdda1 vdda18 vdda18 vdda1 agnd a gnd agnd 11 10 dacclk+ vddapll18 extio vee18n vee18n vssclk vddl2_1 vddl 2_1 vssclk vee18n vee18n sdio 10 9 dacclk- vddapll18 rbias vddavco18 vddavco18 vssclk vddclk 1 vddclk1 vssclk reset\ sclk sdo 9 8 vssclk vssclk atest vddpll1 vddpll1 vssclk vddl1_1 vddl1_1 vssclk alarm sleep sden\ 8 7 clktx+ vddtx18 sync1\+ vdddig1 dgnd vdde1 dgnd vdde1 dgnd gp i0 gpo0 gpi1 7 6 clktx- vddtx1 sync1\- dgnd vdddig1 dgnd vdde1 dgnd vdde1 txe nable gpo1 dgnd 6 5 vdddig1 vdddig1 vdddig1 vdddig1 vdddig1 vdddig1 vdddig1 vd dio18 trst\ tms dgnd rx3+ 5 4 sysref- vdds18 sync0\+ vsense vdddig1 vdddig1 vdddig1 tdi t do tclk dgnd rx3- 4 3 sysref+ vdds18 sync0\- iforce vdddig1 amux1 amux0 vddt1 vdd t1 testmode dgnd rx2- 3 2 dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddr18 vddr18 dgnd dgnd rx2 + 2 1 rx7+ rx7- rx6- rx6+ rx5+ rx5- rx4- rx4+ rx0+ rx0- rx1- rx1+ 1 a b c d e f g h j k l m
5 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions pin i/o description name no. agnd c11, c12, d11, e11, f12, j12, k11, l11, m11, m12, d12, l12 - analog ground. alarm k8 o cmos output for alarm condition. the alarm output functionality is defined through the config7 register. default polarity is active low, but can be changed to active high via config0 alarm_out_pol control bit. amux0 g3 o analog test pin for serdes, lane 0 to lane 3. can be left floating. amux1 f3 o analog test pin for serdes, lane 4 to lane 7. can be left floating. atest c8 o analog test pin for dac, references and pll. can be left floating. clktx+ a7 o divided output clock, self-biased, positive terminal. clktx- a6 o divided output clock, self-biased, negative terminal. dacclk+ a10 i device clock, self-biased, positive terminal. dacclk- a9 i device clock, self-biased, negative terminal. dacclkse a12 i single ended device clock optional input. can be left floating if not used. dgnd a2, b2, c2, d2, d6, e2, e7, f2, f6, g2, g7, h6, j7, k2, l2, l3, l4, l5, m6 - digital ground. extio c10 requires a 0.1 f decoupling capacitor to agnd. gpi0 l6 factory use only. user should gnd. gpi1 m7 factory use only. user should gnd. gpo0 l7 used for cmos sync0\ signal. gpio1 k7 used for cmos sync1\ signal. iforce d3 test pin for on chip parametrics. can be left floating. rbias c9 i/o full-scale output current bias. change the full-scale output current through dacfs in register dacfs ( 8.5.72 ). expected to be 3.6 k to gnd for 40 ma full scale output. reset k9 i active low input for chip reset, which resets all the programming registers to their default state. internal pull-up. rx0+ j1 i cml serdes interface lane 0 input, positive rx0- k1 i cml serdes interface lane 0 input, negative rx1+ m1 i cml serdes interface lane 1 input, positive rx1- l1 i cml serdes interface lane 1 input, negative rx2+ m2 i cml serdes interface lane 2 input, positive rx2- m3 i cml serdes interface lane 2 input, negative rx3+ m5 i cml serdes interface lane 3 input, positive rx3- m4 i cml serdes interface lane 3 input, negative rx4+ h1 i cml serdes interface lane 4 input, positive rx4- g1 i cml serdes interface lane 4 input, negative rx5+ e1 i cml serdes interface lane 5 input, positive rx5- f1 i cml serdes interface lane 5 input, negative rx6+ d1 i cml serdes interface lane 6 input, positive rx6- c1 i cml serdes interface lane 6 input, negative rx7+ a1 i cml serdes interface lane 7 input, positive rx7- b1 i cml serdes interface lane 7 input, negative sclk l9 i serial interface clock. internal pull-down. sden m8 i active low serial data enable, always an input to the dac38rfxx. internal pull-up. sdio m10 i/o serial interface data. bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. internal pull-down. sdo m9 o uni-directional serial interface data output in 4-pin mode. the sdo pin is tri-stated in 3-pin interface mode (default). sleep l8 i active high asynchronous hardware power-down input. internal pull-down. sync0+ c4 o synchronization request to transmitter for jesd204b link 0, lvds positive output. sync0- c3 o synchronization request to transmitter for jesd204b link 0, lvds negative output. sync1+ c7 o synchronization request to transmitter for jesd204b link 1, lvds positive output.
6 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name no. sync1- c6 o synchronization request to transmitter for jesd204b link 1, lvds negative output. sysref+ a3 i lvpecl sysref positive input. this positive/negative pair is captured with the rising edge of dacclkp/n. it is used for multiple dac synchronization. sysref- a4 i lvpecl sysref negative input. (see the sysref description) tclk k4 i jtag test clock. internal pull-down tdi h4 i jtag test data in. internal pull-up tdo j4 o jtag test data out. internal pull-up testmode k3 i this pin is used for factory testing. recommended to connect to ground. tms k5 i jtag test mode select. internal pull-up trst j5 i jtag test reset. must be connected to ground if not used. internal pull-up txenable k6 i transmit enable active high input. internal pull-down. to enable analog output data transmission, pull the cmos txenable pin to high. to disable analog output, pull cmos txenable pin to low. the dac output is forced to midscale. vdda1 f11, j11 i analog 1v supply voltage. vdda18 g11, h11 i analog 1.8v supply voltage. (1.8 v) vddpll1 d8, e8 i analog 1v supply for pll. vddapll18 b9, b10 i pll analog supply voltage. (1.8 v) vddavco18 d9, e9 i analog supply voltage for vco (1.8 v) vddclk1 g9, h9 i internal clock buffer supply voltage (1 v) it is recommended to isolate this supply from vdddig1 and vdda1. vddl1_1 g8, h8 i dac core supply voltage. (1 v) vddl2_1 g10, h10 i dac core supply voltage. (1 v) vdddig1 a5, b5, c5, d5, d7, e3, e4, e5, e6, f4, f5, g4, g5 i digital supply voltage. (1 v) it is recommended to isolate this supply from vddclk1 and vdda1. vdde1 f7, h7, g6, j6 i digital encoder supply voltage (1 v). must be separated from vdddig1 on new substrate device vddio18 h5 i supply voltage for all digital i/o and cmos i/o. vddout18 g12, h12 i dac supply voltage (1.8 v) vddr18 h2, j2 i supply voltage for serdes. (1.8 v) vdds18 b3, b4 i supply voltage for lvds sync0+/- and sync1+/- (1.8v) vddt1 h3, j3 i supply voltage for serdes termination. (1 v) vddtx1 b6 i supply voltage for divided clock output. (1 v) vddtx18 b7 i supply voltage for divided clock output. (1.8 v) vee18n d10, e10, k10, l10 i analog supply voltage. (-1.8 v) vout1 k12 o dac channel 1 single ended output. vout2 e12 o dac channel 2 single ended output. vsense d4 i test pin for on chip parametrics. can be left floating. vssclk a8, a11, b8, b11, b12, f8, f9, f10, j8, j9, j10 - clock ground.
7 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) measured with respect to agnd or dgnd. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage range (2) vdddac1, vdddig1, vddl1_1, vddl2_1, vddclk1, vddt1, vddclk1, vddtx1, vdde1 ? 0.3 1.3 v vddr18, vddio18, vdds18, vddapll18, vddout18, vdda18, vddavco18, vddtx18 ? 0.3 2.45 v vee18n ? 2 ? 0.5 v voltage between agnd and dgnd ? 0.3 0.3 v pin voltage range (2) rx[0..7]+/- ? 0.5 vdddig1 + 0.5 v v sden, sclk, sdio, sdo, txenable, alarm, reset, sleep, tms, tclk, tdi, tdo, trst, testmode, gpi0, gpi1, gpo0, gpo1 ? 0.5 vddio + 0.5 v v clkout+/- ? 0.5 vddtx18 + 0.5 v v dacclk+/-, sysref+/-, dacclkse ? 0.5 vddclk1 + 0.5 v v sync0+/-, sync1+/- ? 0.5 vdds18 + 0.5 v v vout1+/-, vout2+/- ? 0.5 vddaout18 + 0.5 v v rbias, extio, atest ? 0.5 vddaout18 + 0.5 v v iforce, vsense ? 0.5 vdddig1 + 0.5 v v amux1, amux0 ? 0.5 vddt1 + 0.5 v v peak input current (any input) 20 ma peak total input current (all inputs) ? 30 ma junction temperature t j 150 c operating free-air temperature, t a ? 40 85 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 1000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 250 (1) prolonged use at this junction temperature may increase the device failure-in-time (fit) rate 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit t j recommended operating temperature 105 c maximum rated operating junction temperature (1) 125 c t a recommended free-air temperature ? 40 85 c
8 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) aav (fcbga) unit 144 pins r ja junction-to-ambient thermal resistance 25 c/w r jc(top) junction-to-case (top) thermal resistance 1.0 c/w r jb junction-to-board thermal resistance 7.7 c/w jt junction-to-top characterization parameter 0.1 c/w jb junction-to-board characterization parameter 7.7 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w 7.5 electrical characteristics - dc specifications typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, nominal supplies, unless otherwise noted. parameter test conditions min typ max unit dc accuracy resolution 14 bits analog output full scale output signal current 10 30 40 ma p (outfs) full scale output power 50- load 2.1 ghz output frequency 0 dbm output compliance range 1.3 2.3 v reference output v ref reference output voltage 0.9 v reference output current 100 na temperature coefficients reference voltage drift 8 ppm/ c reference voltage drift vdda18, vddapll18, vdds18, vddio18, vddr18, vddapll18, vddout18, vddavco18 1.71 1.8 1.89 v vdddig1 vdda1, vddt1, vddapll1, vddclk1, vddl1_1, vddl2_1, vddtx1, vdde1 0.95 1 1.05 v vee18n ? 1.89 ? 1.8 ? 1.71 v power supply current and consumption 1 v digital supplies: vdddig1 mode 1: 2 tx, 1iq/slice, lmfs = 8411, pll on, 12x interpolation, f input = 737.28 msps, f dac = 8847.36 msps, nco ? s = 2.14 ghz, clktx disabled 1478 2290 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1510 1758 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 281 290 ma -1.8 v supply: vee18n 159 180 ma p dis power dissipation 3779 4894 mw 1 v digital supplies: vdddig1 mode 2: 1 tx, 1iq/slice, lmfs = 4211, pll on, 12x interpolation, f input = 737.28 msps, f dac = 8847.36 msps, nco = 2.14 ghz, clktx disabled 1110 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1303 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 257 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 3162 mw
9 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - dc specifications (continued) typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, nominal supplies, unless otherwise noted. parameter test conditions min typ max unit 1v digital supplies: vdddig1 mode 3: 2 tx, 2 iq/slice, lmfs = 8821, pll on, 24x interpolation, f input = 368.64 msps, f dac = 8847.36 msps, nco1 = 1.84 ghz, nco2 = 2.15 ghz, clktx disabled 2253 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1522 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 280 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 4565 mw 1 v digital supplies: vdddig1 mode 4: 1 tx, 2 iq/slice, lmfs = 4421, pll on, 24x interpolation, f input = 368.64 msps, f dac = 8847.36 msps, nco1 = 1.84 ghz, nco2 = 2.15 ghz, clktx disabled 1701 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1314 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 256 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 3763 mw 1 v digital supplies: vdddig1 mode 5: 2 tx, 1 iq/slice, lmfs = 4421, pll on, 18x interpolation, f input = 491.52 msps, f dac = 8847.36 msps, nco1 = 2.14 ghz, clktx disabled 1328 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1312 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 249 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 3374 mw 1 v digital supplies: vdddig1 mode 6: 1 tx, 1 iq/slice, lmfs = 2221, pll on, 18x interpolation, f input = 491.52 msps, f dac = 8847.36 msps, nco1 = 2.14 ghz, clktx disabled 1027 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1206 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 248 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 2964 mw 1 v digital supplies: vdddig1 mode 7: 2 tx, 1 iq/slice, lmfs = 8411, pll on, 6x interpolation, f input = 983.04 msps, f dac = 5898.24 msps, nco1 = 2.14 ghz, clktx disabled 1157 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1125 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 246 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 3011 mw 1 v digital supplies: vdddig1 mode 8: 1 tx, 1 iq/slice, lmfs = 4211, pll on, 6x interpolation, f input = 983.04 msps, f dac = 5898.24 msps, nco1 = 2.14 ghz, clktx disabled 848 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 647 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 230 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 2195 mw
10 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - dc specifications (continued) typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, nominal supplies, unless otherwise noted. parameter test conditions min typ max unit 1 v digital supplies: vdddig1 mode 9: 2 tx, 2 iq/slice, lmfs = 4831, pll on, 24x interpolation, f inpu t = 368.64 msps, f dac = 8847.36 msps, nco1 = 2.14 ghz, clktx disabled 2131 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1324 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 251 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 4192 mw 1 v digital supplies: vdddig1 mode 10: 1 tx, 2 iq/slice, lmfs = 2431, pll on, 24x interpolation, f input = 368.64 msps, f dac = 8847.36 msps, nco1 = 2.14 ghz, clktx disabled 1635 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 1212 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 250 ma -1.8 v supply: vee18n 159 ma p dis power dissipation 3583 mw 1 v digital supplies: vdddig1 mode 11: power down mode, no clock, dacs in sleep, serdes in sleep 63 568 ma 1 v analog supplies: vdda1 vddaclk1 vddtx1 vddapll1 vddt1 vdde1 18 105 ma 1.8 v supplies: vdda18 vddout18 vddavco18 vddapll18 vddr18 vddio18 vdds18 vddtx18 47 51 ma -1.8 v supply: vee18n 23 28 ma p dis power dissipation 208 815 mw vddtx1 f dac = 8847 msps, clock out divider enabled 25 ma f dac = 5898 msps, clock out divider enabled 19 ma vddtx18 clock out enabled 16 ma
11 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6 electrical characteristics - digital specifications typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, external differential clock mode at 9 gsps, 12x interpolation, f out = 2.14 ghz, i (outfs) = 40 ma, nominal supplies, lmfshd = 84111, unless otherwise noted. parameter test conditions min typ max unit cml serdes inputs: rx[7:0]+/- v diff receiver input amplitude 50 1200 mv v com input common mode voltage term = 111 600 mv term = 001 700 term = 100 0 term = 101 250 z ddiff internal differential termination 85 100 115 f serdes serdes bit rate 0.78125 12.5 gbps differential clock inputs: sysref+/-, dacclk+/- f dacclk dacclk input frequency 0.1 9 ghz v com differential input common mode voltage 0.5 v v i(dpp) differential input peak-to-peak voltage 800 2000 mv z t internal termination 100 c l input capacitance 2 pf duty cycle (dacclk only) 40% 60% lvds output: sync0+/-, sync1+/- v com output common mode voltage 1.2 v z t internal termination 100 v od differential output voltage swing 500 mv cml output: clktx+/- v od cml output: clktx+/- 1300 mv cmos interface: sden, sclk, sdio, sdo, txenable, alarm, reset, sleep, tms, tclk, tdi, tdo, trst, testmode, syncse1, syncse2 v ih high-level input voltage 0.7 x vddio v v il low-level input voltage 0.3 x vddio v i ih high-level input current ? 40 40 a i ol low-level input current ? 40 40 a c i cmos input capacitance 2 pf v oh high-level output voltage i load = ? 100 a vddio ? 0.2 v i load = ? 2 ma 0.8 x vddio v ol low-level output voltage i load = ? 100 a 0.2 v i load = ? 2 ma 0.5 latency rx serdes digital delay full rate, rate = ? 00 ? 34 ui half rate, rate = ? 01 ? 29 quarter rate, rate = ? 10 ? 26.5 eighth rate, rate = ? 11 ? 26.25 serdes output to jed204b elastic buffer input latency 21 -39 jesd clock cycles
12 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - digital specifications (continued) typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, external differential clock mode at 9 gsps, 12x interpolation, f out = 2.14 ghz, i (outfs) = 40 ma, nominal supplies, lmfshd = 84111, unless otherwise noted. parameter test conditions min typ max unit digital latency: jesd buffer to dac output lmfshd = 82121, 6x interpolation 856 dac clock cycles lmfshd = 82121, 8x interpolation 1120 lmfshd = 82121, 12x interpolation 1602 lmfshd = 82121, 16x interpolation 2091 lmfshd = 42111 or 84111, 6x interpolation 817 lmfshd = 42111 or 84111, 8x interpolation 1057 lmfshd = 42111 or 84111, 10x interpolation 1184 lmfshd = 42111 or 84111, 12x interpolation 1532 lmfshd = 42111 or 84111, 16x interpolation 1997 lmfshd = 42111 or 84111, 18x interpolation 2142 lmfshd = 42111 or 84111, 24x interpolation 2941 lmfshd = 22210 or 44210, 8x interpolation 1020 lmfshd = 22210 or 44210, 12x interpolation 1473 lmfshd = 22210 or 44210, 16x interpolation 1917 lmfshd = 22210 or 44210, 18x interpolation 2050 lmfshd = 22210 or 44210, 20x interpolation 2275 lmfshd = 22210 or 44210, 24x interpolation 2821 lmfshd = 12410 or 24410, 16x interpolation 1912 lmfshd = 12410 or 24410, 24x interpolation 2786 lmfshd = 44210 or 88210, 8x interpolation 916 lmfshd = 44210 or 88210, 12x interpolation 1317 lmfshd = 44210 or 88210, 16x interpolation 1709 lmfshd = 44210 or 88210, 24x interpolation 2509 lmfshd = 24410 or 48410, 16x interpolation 1672 lmfshd = 24410 or 48410, 24x interpolation 1593
13 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - digital specifications (continued) typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, external differential clock mode at 9 gsps, 12x interpolation, f out = 2.14 ghz, i (outfs) = 40 ma, nominal supplies, lmfshd = 84111, unless otherwise noted. parameter test conditions min typ max unit sysref to jesd lmfc reset lmfshd = 82121, 6x interpolation 5 jesd clock cycles lmfshd = 82121, 8x interpolation 5 lmfshd = 82121, 12x interpolation 5 lmfshd = 82121, 16x interpolation 5 lmfshd = 42111 or 84111, 6x interpolation 16 lmfshd = 42111 or 84111, 8x interpolation 16 lmfshd = 42111 or 84111, 10x interpolation 15 lmfshd = 42111 or 84111, 12x interpolation 15 lmfshd = 42111 or 84111, 16x interpolation 13 lmfshd = 42111 or 84111, 18x interpolation 15 lmfshd = 42111 or 84111, 24x interpolation 15 lmfshd = 22210 or 44210, 8x interpolation 8 lmfshd = 22210 or 44210, 12x interpolation 7 lmfshd = 22210 or 44210, 16x interpolation 6 lmfshd = 22210 or 44210, 18x interpolation 7 lmfshd = 22210 or 44210, 20x interpolation 5 lmfshd = 22210 or 44210, 24x interpolation 4 lmfshd = 12410 or 24410, 16x interpolation 9 lmfshd = 12410 or 24410, 24x interpolation 7 lmfshd = 44210 or 88210, 8x interpolation 29 lmfshd = 44210 or 88210, 12x interpolation 27 lmfshd = 44210 or 88210, 16x interpolation 26 lmfshd = 44210 or 88210, 24x interpolation 25 lmfshd = 24410 or 48410, 16x interpolation 8 lmfshd = 24410 or 48410, 24x interpolation 6 latency nco dac clock cycles inverse sinc multi-band summation pa protection pll/vco f vco vco operating frequency dac38rf86/96 7.96 9 ghz dac38rf87/97 5.24 6.72 ghz
14 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.7 electrical characteristics - ac specifications typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, external differential clock mode at 9 gsps, 12x interpolation, f out = 2.14 ghz, i (outfs) = 40 ma, nominal supplies, lmfshd = 84111, unless otherwise noted. parameter test conditions min typ max unit analog output f dac maximum dac sample rate 9 gsps ac performance - cw sfdr spurious free dynamic range 0 ? f dac /2 f clk = 6 ghz , f out = 501 mhz 70 dbc f clk = 6 ghz , f out = 951 mhz 67 f clk = 6 ghz , f out = 1851 mhz 59 f clk = 6 ghz , f out = 2651 mhz 57 f clk = 9 ghz , f out = 501 mhz 64 f clk = 9 ghz , f out = 951 mhz 65 f clk = 9 ghz , f out = 1851 mhz 62 f clk = 9 ghz , f out = 2651 mhz 50 f clk = 9 ghz , f out = 3651 mhz 51 sfdr spurious free dynamic range within 500 mhz f out 250 mhz f clk = 6 ghz , f out = 501 mhz 94 dbc f clk = 6 ghz , f out = 951 mhz 88 f clk = 6 ghz , f out = 1851 mhz 87 f clk = 6 ghz , f out = 2651 mhz 78 f clk = 9 ghz , f out = 501 mhz 92 f clk = 9 ghz , f out = 951 mhz 88 f clk = 9 ghz , f out = 1851 mhz 85 f clk = 9 ghz , f out = 2651 mhz 82 f clk = 9 ghz , f out = 3651 mhz 78 sfdr spurious free dynamic range excluding hd2, hd3 and cmp2 0 ? f dac /2 f clk = 6 ghz , f out = 501 mhz 72 dbc f clk = 6 ghz , f out = 951 mhz 75 f clk = 6 ghz , f out = 1851 mhz 75 f clk = 6 ghz , f out = 2651 mhz 71 f clk = 9 ghz , f out = 501 mhz 63 f clk = 9 ghz , f out = 951 mhz 66 f clk = 9 ghz , f out = 1851 mhz 65 f clk = 9 ghz , f out = 2651 mhz 64 f clk = 9 ghz , f out = 3651 mhz 62 hd2 2nd order harmonic f clk = 6 ghz , f out = 501 mhz 71 dbc f clk = 6 ghz , f out = 951 mhz 68 f clk = 6 ghz , f out = 1851 mhz 59 f clk = 6 ghz , f out = 2651 mhz 57 f clk = 9 ghz , f out = 501 mhz 71 f clk = 9 ghz , f out = 951 mhz 67 f clk = 9 ghz , f out = 1851 mhz 62 f clk = 9 ghz , f out = 2651 mhz 49 f clk = 9 ghz , f out = 3651 mhz 51 hd3 3rd order harmonic f clk = 6 ghz , f out = 501 mhz 75 dbc f clk = 6 ghz , f out = 951 mhz 72 f clk = 6 ghz , f out = 1851 mhz 72 f clk = 6 ghz , f out = 2651 mhz 70 f clk = 9 ghz , f out = 501 mhz 74 f clk = 9 ghz , f out = 951 mhz 73 f clk = 9 ghz , f out = 1851 mhz 72 f clk = 9 ghz , f out = 2651 mhz 69 f clk = 9 ghz , f out = 3651 mhz 69
15 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - ac specifications (continued) typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, external differential clock mode at 9 gsps, 12x interpolation, f out = 2.14 ghz, i (outfs) = 40 ma, nominal supplies, lmfshd = 84111, unless otherwise noted. parameter test conditions min typ max unit cmp2 fs/2 clock mixing product (fs/2 ? f out ) f clk = 6 ghz , f out = 501 mhz 79 dbc f clk = 6 ghz , f out = 951 mhz 80 f clk = 6 ghz , f out = 1851 mhz 76 f clk = 6 ghz , f out = 2651 mhz 76 f clk = 9 ghz , f out = 501 mhz 70 f clk = 9 ghz , f out = 951 mhz 67 f clk = 9 ghz , f out = 1851 mhz 67 f clk = 9 ghz , f out = 2651 mhz 63 f clk = 9 ghz , f out = 3651 mhz 59 cmp4+ fs/n (n = 4, 8, 16) clock mixing product (f out fs/n) f clk = 6 ghz , f out = 501 mhz 90 dbc f clk = 6 ghz , f out = 951 mhz 87 f clk = 6 ghz , f out = 1851 mhz 83 f clk = 6 ghz , f out = 2651 mhz 76 f clk = 9 ghz , f out = 501 mhz 91 f clk = 9 ghz , f out = 951 mhz 88 f clk = 9 ghz , f out = 1851 mhz 85 f clk = 9 ghz , f out = 2651 mhz 81 f clk = 9 ghz , f out = 3651 mhz 74 imd3 third-order two-tone intermodulation distortion f clk = 6 ghz , f out = 501 5 mhz, ? 6 dbfs each tone 83 dbc f clk = 6 ghz , f out = 951 5 mhz, ? 6 dbfs each tone 79 f clk = 6 ghz , f out = 1851 5 mhz, ? 6 dbfs each tone 76 f clk = 6 ghz , f out = 2651 5 mhz, ? 6 dbfs each tone 75 f clk = 9 ghz , f out = 501 5 mhz, ? 6 dbfs each tone 84 f clk = 9 ghz , f out = 951 5 mhz, ? 6 dbfs each tone 80 f clk = 9 ghz , f out = 1851 5 mhz, ? 6 dbfs each tone 74 f clk = 9 ghz , f out = 2651 5 mhz, ? 6 dbfs each tone 73 f clk = 9 ghz , f out = 3651 5 mhz, ? 6 dbfs each tone 71 nsd noise spectral density > 50 mhz offset f clk = 6 ghz , f out = 501 mhz ? 169 dbfs/hz f clk = 6 ghz , f out = 951 mhz ? 163 f clk = 6 ghz , f out = 1851 mhz ? 155 f clk = 6 ghz , f out = 2651 mhz ? 154 f clk = 9 ghz , f out = 501 mhz ? 171 f clk = 9 ghz , f out = 951 mhz ? 167 f clk = 9 ghz , f out = 1851 mhz ? 156 f clk = 9 ghz , f out = 2651 mhz ? 155 f clk = 9 ghz , f out = 3651 mhz ? 153 f clk = 6 ghz , f out = 501 mhz, ? 9 dbfs ? 160 f clk = 6 ghz , f out = 951 mhz, ? 9 dbfs ? 154 f clk = 6 ghz , f out = 1851 mhz, ? 9 dbfs ? 150 f clk = 9 ghz , f out = 2651 mhz, ? 9 dbfs ? 153 f clk = 9 ghz , f out = 3651 mhz, ? 9 dbfs ? 150
16 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics - ac specifications (continued) typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, external differential clock mode at 9 gsps, 12x interpolation, f out = 2.14 ghz, i (outfs) = 40 ma, nominal supplies, lmfshd = 84111, unless otherwise noted. parameter test conditions min typ max unit nsd (on-chip pll) noise spectral density > 50 mhz offset on-chip pll enabled f clk = 6 ghz , f out = 501 mhz ? 161 dbfs/hz f clk = 6 ghz , f out = 951 mhz ? 160 f clk = 6 ghz , f out = 1851 mhz ? 156 f clk = 6 ghz , f out = 2651 mhz ? 151 f clk = 9 ghz , f out = 501 mhz ? 171 f clk = 9 ghz , f out = 951 mhz ? 166 f clk = 9 ghz , f out = 1851 mhz ? 156 f clk = 9 ghz , f out = 2651 mhz ? 156 f clk = 9 ghz , f out = 3651 mhz ? 153 f clk = 6 ghz , f out = 501 mhz, ? 9 dbfs ? 154 f clk = 6 ghz , f out = 951 mhz, ? 9 dbfs ? 154 f clk = 6 ghz , f out = 1851 mhz, ? 9 dbfs ? 151 f clk = 9 ghz , f out = 2651 mhz, ? 9 dbfs ? 153 f clk = 9 ghz , f out = 3651 mhz, ? 9 dbfs ? 151 isolation isolation between dac a and dac b analog output < 2 ghz 55 dbc > 2 ghz to 4 ghz 54 ac performance ? modulated signals acpr wcdma 1 carrier adjacent channel power ratio f clk = 5898.24 mhz , f out = 950 mhz 78 dbc f clk = 5898.24 mhz, f out = 2140 mhz 73 f clk = 8847.36 mhz , f out = 950 mhz 77 f clk = 8847.36 mhz, f out = 2140 mhz 73 alt-aclr wcdma 1 carrier alternate channel acpr f clk = 5898.24 mhz , f out = 950 mhz 83 dbc f clk = 5898.24 mhz, f out = 2140 mhz 77 f clk = 8847.36 mhz , f out = 950 mhz 82 f clk = 8847.36 mhz, f out = 2140 mhz 78 lte20 20 mhz lte adjacent channel power ratio f clk = 5898.24 mhz , f out = 800 mhz 74 dbc f clk = 5898.24 mhz, f out = 2650 mhz 68 f clk = 8847.36 mhz , f out = 800 mhz 74 f clk = 8847.36 mhz, f out = 2650 mhz 68 f clk = 8847.36 mhz, f out = 3700 mhz 66 ac performance ? modulated signals, on-chip pll enabled acpr wcdma 1 carrier adjacent channel power ratio f clk = 5898.24 mhz , f out = 950 mhz 77 dbc f clk = 5898.24 mhz, f out = 2140 mhz 73 f clk = 8847.36 mhz , f out = 950 mhz 75 f clk = 8847.36 mhz, f out = 2140 mhz 69 alt-aclr wcdma 1 carrier alternate channel acpr f clk = 5898.24 mhz , f out = 950 mhz 82 dbc f clk = 5898.24 mhz, f out = 2140 mhz 78 f clk = 8847.36 mhz , f out = 950 mhz 81 f clk = 8847.36 mhz, f out = 2140 mhz 77 lte20 20 mhz lte adjacent channel power ratio f clk = 5898.24 mhz , f out = 800 mhz 75 dbc f clk = 5898.24 mhz, f out = 2650 mhz 69 f clk = 8847.36 mhz , f out = 800 mhz 73 f clk = 8847.36 mhz, f out = 2650 mhz 67 f clk = 8847.36 mhz, f out = 3700 mhz 64
17 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.8 timing requirements min nom max unit digital input timing specifications timing: sysref+/- t s(sysref) setup time, sysref+/- valid to rising edge of dacclk+/- sysref capture assist disabled 50 ps t h(sysref) hold time, sysref+/- valid after rising edge of dacclk+/- sysref capture assist disabled 50 ps timing: serial port t s(/sden) setup time, sden to rising edge of sclk 20 ns t s(sdio) setup time, sdio valid to rising edge of sclk 10 ns t h(sdio) hold time, sdio valid after rising edge of sclk 5 ns t (sclk) period of sclk temperature sensor read 1 s all other registers 100 ns t d(data) data output delay after falling edge of sclk 25 ns t reset minimum reset pulse width 25 ns analog output t s(dac) output settling time to 0.1% 1 ns t r output rise time 10% to 90% 50 ns t f output fall time 90% to 10% 50 ns latency rx serdes analogdelay 250 ps dac wake-up time i out current settling to 1% of i outfs from deep sleep 90 s dac sleep time i out current settling to less than 1% of i outfs in deep sleep 90 s
18 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.9 typical characteristics unless otherwise noted, all plots are at t a = 25 c, nominal supply voltages, f dac = 8847.36msps, 12x interpolation, 0dbfs digital input, 40 ma full scale output current , lmfshd = 84111 and pll is disabled. measured 50 mhz from carrier figure 1. nsd vs output frequency over input scale measured 50 mhz from carrier figure 2. nsd vs output frequency over output current i out fs measured 50 mhz from carrier figure 3. nsd vs output frequency over clocking option figure 4. hd2 vs output frequency over input scale output frequency (mhz) nsd (dbc/hz) 500 1000 1500 2000 2500 3000 3500 4000 4500 120 125 130 135 140 145 150 155 160 165 170 d029d029 on-chip pll external clock output frequency (mhz) hd2 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d018 -12dbfs -6dbfs 0dbfs output frequency (mhz) nsd (dbc/hz) 500 1000 1500 2000 2500 3000 3500 4000 4500 120 125 130 135 140 145 150 155 160 165 170 d020 -12dbfs -9dbfs -6dbfs 0dbfs output frequency (mhz) nsd (dbc/hz) 500 1000 1500 2000 2500 3000 3500 4000 4500 120 125 130 135 140 145 150 155 160 165 170 d025 iout=40ma iout=30ma iout=20ma iout=10ma
19 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) unless otherwise noted, all plots are at t a = 25 c, nominal supply voltages, f dac = 8847.36msps, 12x interpolation, 0dbfs digital input, 40 ma full scale output current , lmfshd = 84111 and pll is disabled. figure 5. hd2 vs output frequency over output current i out fs figure 6. hd2 vs output frequency over clocking option figure 7. hd3 vs output frequency over input scale figure 8. hd3 vs output frequency over output current i out fs figure 9. hd3 vs output frequency over clocking option excludes hd2, hd3 and cmp2 figure 10. sfdr vs output frequency over input scale output frequency (mhz) hd3 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d015 on-chip pll external clock output frequency (mhz) sfdr (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d001d032 -12dbfs -6dbfs 0dbfs output frequency (mhz) hd3 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 d013 -12dbfs -6dbfs 0dbfs output frequency (mhz) hd3 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 d014 iout=10ma iout=20ma iout=30ma iout=40ma output frequency (mhz) hd2 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d023d008d023 iout=10ma iout=20ma iout=30ma iout=40ma output frequency (mhz) hd2 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d027 on-chip pll external clock
20 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) unless otherwise noted, all plots are at t a = 25 c, nominal supply voltages, f dac = 8847.36msps, 12x interpolation, 0dbfs digital input, 40 ma full scale output current , lmfshd = 84111 and pll is disabled. excludes hd2, hd3 and cmp2 figure 11. sfdr vs output frequency over output current i out fs excludes hd2, hd3 and cmp2 figure 12. sfdr vs output frequency over clocking option +/- 250mhz span figure 13. sfdr vs output frequency over input scale 250 mhz span figure 14. sfdr vs output frequency over output current i out fs +/- 250mhz span figure 15. sfdr vs output frequency over clocking option figure 16. imd3 vs output frequency over input scale output frequency (mhz) sfdr (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d026 on-chip pll external clock output frequency (mhz) sfdr (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 85 90 95 100 d026 on-chip pll external clock output frequency (mhz) imd3 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 85 90 d006 -18dbfs -12dbfs -6dbfs 0dbfs output frequency (mhz) sfdr (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 85 90 95 100 d032 -12dbfs -6dbfs 0dbfs output frequency (mhz) sfdr (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 85 90 95 100 d008 iout=10ma iout=20ma iout=30ma iout=40ma output frequency (mhz) sfdr (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d022 iout=10ma iout=20ma iout=30ma iout=40ma
21 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) unless otherwise noted, all plots are at t a = 25 c, nominal supply voltages, f dac = 8847.36msps, 12x interpolation, 0dbfs digital input, 40 ma full scale output current , lmfshd = 84111 and pll is disabled. figure 17. imd3 vs output frequency over output current i out fs figure 18. imd3 vs output frequency over clocking option figure 19. power vs output frequency output frequency (mhz) output power (dbm) 0 500 1000 1500 2000 2500 3000 3500 4000 4500 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 d017 output frequency (mhz) hd3 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d007d007 iout=10ma iout=20ma iout=30ma iout=40ma output frequency (mhz) imd3 (dbc) 500 1000 1500 2000 2500 3000 3500 4000 4500 35 40 45 50 55 60 65 70 75 80 d030 on-chip pll external clock
22 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) unless otherwise noted, all plots are at t a = 25 c, nominal supply voltages, f dac = 8847.36msps, 12x interpolation, 0dbfs digital input, 40 ma full scale output current , lmfshd = 84111 and pll is disabled. vco frequency = 8.85 ghz measured at 1.8 ghz dac38rf86 /96 only figure 20. vco phase noise vs offset frequency over charge pump current vco frequency = 8.85 ghz dac38rf86/96 only figure 21. vco1 output clock phase noise vs offset frequency over divider ratio vco frequency = 5.9 ghz measured at 1.8 ghz dac38rf87/97 only figure 22. vco phase noise vs offset frequency over charge pump current vco frequency = 5.9 ghz dac38rf87/97 only figure 23. vco output clock phase noise vs offset frequency over divider ratio freq offset (hz) phase noise (dbc) 1000 10000 100000 1000000 1e+7 5e+7 -160 -150 -140 -130 -120 -110 -100 -90 d005 cp=1 cp=2 cp=3 cp=4 cp=5 cp=6 cp=7 cp=8 cp=9 cp=10 cp=11 cp=12 cp=13 cp=14 cp=15 freq offset (hz) phase noise (dbc) 1000 10000 100000 1000000 1e+7 5e+7 -160 -150 -140 -130 -120 -110 -100 d006 div4 div3 div2 freq offset (hz) phase noise (dbc) 1000 10000 100000 1000000 1e+7 5e+7 -160 -140 -120 -100 -80 -60 d007 cp=1 cp=2 cp=3 cp=4 cp=5 cp=6 cp=7 cp=8 cp=9 cp=10 cp=11 cp=12 cp=13 cp=14 cp=15 freq offset (hz) phase noise (dbc) 1000 10000 100000 1000000 1e+7 5e+7 -160 -150 -140 -130 -120 -110 -100 -90 d008 div4 div3 div2
23 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the dac38rfxx are a family of high performance 14-bit, 9 gsps interpolating digital-to-analog converter (dacs), capable of synthesizing wideband signals from 0 to 4 ghz in 1st nyquist zone and up to 6 ghz in 2nd nyquist zone. a high dynamic range allows the dac38rfxx to generate 2g/3g/4g signals for wireless basestations for all 3gpp bands, including simultaneous generation of multiple bands. the devices have a low power 8 lane jesd204b interface, with a maximum bit rate of 12.5 gbps. the full output rate is achieved by use of the interpolation filters, after which the signal can be upconverted to rf using a digital nco and digital quadrature modulator. two signals can be tuned to different frequencies and digitally combined, allowing wide output spectrums. an optional low jitter pll/vco simplifies the dac clock generation by allowing use of a lower frequency reference clock. 8.2 functional block diagrams figure 24. dac38rf86, dac38rf87 block diagram 14-b dac control interface temp sensor clock distribution rbias dacclk+ dacclk- rx[4..7]+ rx[4..7]- rx[0..3]+ rx[0..3]- sysref+ sysref- sdo sdio sdenb sclk txenable resetb vddclk1 vdddig1 vdda18 gnd dacb gain low jitter pll alarm sleep sync1\+ sync1\- testmode vddavco18 vddapll1 vddio18 0.9 v ref vdda1 vdds18 vddt1 vddr18 jtag tclk tdi tdo tms trst\ atest amux0/1 iforce vsense testmode vee18n vout2 clktx+ divider /2, /3, /4 jesd interface multi-band duc channel 1 (multi-duc1) x sin(x) 14-b dac daca gain vout1 x sin(x) i q i q i q i q nco 1 nco 2 nco 4 nco 3 multi-band duc channel 2 (multi-duc2) clktx- vddapll18 sync2\+ sync2\- gpo0 gpo1 gpi0 gpi1 vddl1_1 vddl2_1 dacclkse vddtx1 vddtx18 vddout18 copyright ? 2016, texas instruments incorporated extio
24 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated functional block diagrams (continued) figure 25. dac38rf96, dac38rf97 block diagram 14-b dac control interface temp sensor clock distribution dacclk+ dacclk- rx[4..7]+ rx[4..7]- rx[0..3]+ rx[0..3]- sysref+ sysref- sdo sdio sdenb sclk txenable resetb vddclk1 vdddig1 vdda18 gnd dacb gain low jitter pll alarm sleep sync1\+ sync1\- testmode vddavco18 vddapll1 vddio18 vdda1 vdds18 vddt1 vddr18 jtag tclk tdi tdo tms trst\ atest amux0/1 iforce vsense vee18n vout2 clktx+ divider /2, /3, /4 jesd interface single-band duc channel 1 x sin(x) 14-b dac daca gain vout1 x sin(x) i q i q nco 1 nco 2 single-band duc channel 2 clktx- vddapll18 sync2\+ sync2\- gpo0 gpo1 gpi0 gpi1 vddl1_1 vddl2_1 dacclkse vddtx1 vddtx18 vddout18 copyright ? 2016, texas instruments incorporated rbias 0.9 v ref testmode extio
25 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3 feature description 8.3.1 serdes inputs the dac38rfxx rx [0..7]+/- differential inputs are each internally terminated to a common point via 50 , as shown in figure 26 . figure 26. serial lane input termination common mode termination is via a 50 pf capacitor to gnd. the common mode voltage and termination of the differential signal can be controlled in a number of ways to suit a variety of applications via field term in register srds_cfg2 ( 8.5.87 ), as described in table 1 . note ac coupling is recommended for jesd204b compliance. table 1. receiver termination selection term effect 000 reserved 001 common point set to 0.7 v. this configuration is for ac coupled systems. the transmitter has no effect on the receiver common mode, which is set to optimize the input sensitivity of the receiver. note: this mode is not compatible with jesd204b. 01x reserved 100 common point set to gnd. this configuration is for applications that require a 0 v common mode. 101 common point set to 0.25 v. this configuration is for applications that require a low common mode. 110 reserved 111 common point floating. this configuration is for dc coupled systems in which the common mode voltage is set by the attached transmit link partner to 0 and 0.6 v. note: this mode is not compatible with jesd204b input data is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm. the polarity of rx+ and rx- can be inverted by setting the bit of the corresponding lane in field invpair in register srds_pol ( 8.5.88 ) to ? 1 ? . this can potentially simplify pcb layout and improve signal integrity by avoiding the need to swap over the differential signal traces. due to processing effects, the devices in the rx+ and rx- differential sense amplifiers will not be perfectly matched and there will be some offset in switching threshold. the dac38rfxx contains circuitry to detect and correct for this offset. this feature can be enabled by setting enoc in register srds_cfg1 ( 8.5.86 ) to ? 1 ? . it is anticipated the most users will enable this feature. during the compensation process, loopback in register srds_cfg1 ( 8.5.86 ) must be set to ? 00 ? .
26 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.2 serdes rate the dac38rfxx has eight configurable jesd204b serial lanes. the highest speed of each serdes lane is 12.5 gbps. because the primary operating frequency of the serdes is determined by its reference clock and pll multiplication factor, there is a limit on the lowest serdes rate supported. to support lower speed application, each receiver should be configured to operate at half, quarter or eighth of the full rate via field rate in register srds_cfg2 ( 8.5.87 ). refer to table 2 for details. table 2. lane rate selection rate effect 00 full rate. four data samples taken per serdes pll output clock cycle. 01 half rate. two data samples taken per serdes pll output clock cycle. 10 quarter rate. one data samples taken per serdes pll output clock cycle. 11 eighth rate. one data samples taken every two serdes pll output clock cycles. 8.3.3 serdes pll the dac38rfxx has two integrated plls, one pll is to provide the clocking of dac; the other pll is to provide the clocking for the high speed serdes. the reference frequency of the serdes pll can be in the range of 100- 800 mhz nominal, and 300-800 mhz optimal. the reference frequency is derived from dacclk divided down by the value in field serdes_refclk_div in register srds_clk_cfg ( 8.5.84 ), as shown in figure 27 . field serdes_clk_sel in register srds_clk_cfg ( 8.5.84 ) determines if the dacclk input or dac pll output is used as the source of the serdes pll reference. if the dacclk input is used, a pre-divider set by field serdes_refclk_prediv in register srds_clk_cfg ( 8.5.84 ) should be used to reduce the frequency of the dacclk. figure 27. reference clock of serdes pll during normal operation, the clock generated by pll is 4-25 times the reference frequency, according to the multiply factor selected via the field mpy] in register srds_pll_cfg ( 8.5.85 ). in order to select the appropriate multiply factor and reference clock frequency, it is first necessary to determine the required pll output clock frequency. the relationship between the pll output clock frequency and the lane rate is determined by field rate in register srds_cfg2 ( 8.5.87 ) is shown in table 3 . having computed the pll output frequency, the reference frequency can be obtained by dividing this by the multiply factor specified via mpy. dacclk+ dacclk- dacclkse 01 sel_extclk_diffse dac pll predivider 01 serdes_refclk_sel divider serdes_refclk_div serdes_refclk_prediv serdes pll refclk
27 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table 3. rate line rate pll output frequency 00 x gbps 0.25x ghz 01 x gbps 0.5x ghz 10 x gbps 1x ghz 11 x gbps 2x ghz table 4. serdes pll modes selection mpy effect 00010000 4x 00010100 5x 00011000 6x 00100000 8x 00100001 8.25x 00101000 10x 00110000 12x 00110010 12.5x 01000000 15x 01000010 16x 01010000 20x 01011000 22x 01100100 25x other codes reserved the wide range of multiply factors combined with the different rate modes means it is often possible to achieve a given line rate from multiple different reference frequencies. the configuration which utilizes the highest reference frequency achievable is always preferable. the serdes pll vco must be in the nominal range of 1.5625 - 3.125 ghz. it is necessary to adjust the loop filter depending on the operating frequency of the vco. if the pll output frequency is below 2.17 ghz, vrange in register srds_pll_cfg ( 8.5.84 ) should be set high. performance of the integrated pll can be optimized according to the jitter characteristics of the reference clock by setting the appropriate loop bandwidth via field lb in register srds_pll_cfg ( 8.5.84 ). the loop bandwidth is obtained by dividing the reference frequency by bwscale, where the bwscale is a function of both lb and pll output frequency as shown in table 5 . table 5. serdes pll loop bandwidth selection lb effect bwscale vs pll output frequency 3.125 ghz 2.17 ghz 1.5625 ghz 00 medium loop bandwidth 13 14 16 01 ultra high loop bandwidth 7 8 8 10 low loop bandwidth 21 23 30 11 high loop bandwidth 10 11 14 an approximate loop bandwidth of 8 ? 30 mhz is suitable and recommended for most systems where the reference clock is via low jitter clock input buffer. for systems where the reference clock is via a low jitter input cell, but of low quality, an approximate loop bandwidth of less than 8 mhz may offer better performance. for systems where the reference clock is cleaned via an ultra-low jitter lc-based cleaner pll, a high loop bandwidth up to 60 mhz is more appropriate. note that the use of ultra-high loop bandwidth setting is not recommended for pll multiply factor of less than 8. a free running clock output is available when field endivclk in register srds_pll_cfg ( 8.5.85 ) is set high. it runs at a fixed divided-by-80 of the pll output frequency and can be output on the alarm pin by setting field dtest to ? 0001 ? (lanes 0 ? 3) or ? 0010 ? (lanes 4 ? 7) in register dtest ( 8.5.76 ).
28 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.4 serdes equalizer all channels of the dac38rfxx incorporate an adaptive equalizer, which can compensate for channel insertion loss by attenuating the low frequency components with respect to the high frequency components of the signal, thereby reducing inter-symbol interference. figure 28 shows the response of the equalizer, which can be expressed in terms of the amount of low frequency gain and the frequency up to which this gain is applied (i.e., the frequency of the ? zero ? ). above the zero frequency, the gain increases at 6 db/octave until it reaches the high frequency gain. figure 28. equalizer frequency response the equalizer can be configured via fields eq and eqhld in register srds_cfg1 ( 8.5.86 ). table 6 and table 7 summarize the options. when enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether the low frequency gain should be increased or decreased. the decision logic is implemented as a voting algorithm with a relatively long analysis interval. the slow time constant that results reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable response of the channel. the lock time for the adaptive equalizer is data dependent, and so it is not possible to specify a generally applicable absolute limit. however, assuming random data, the maximum lock time will be 6x106 divided by the cdr activity level. for field cdr in register srds_cfg1 ( 8.5.86 ) = 110, the activity level is 1.5 x 10 6 ui. when eq = 0, finer control of gain boost is available using the eqboost ieee1500 tuning chain field, as shown in table 8 . table 6. receiver equalization configuration eq effect [1-0] 00 no equalization. the equalizer provides a flat response at the maximum gain. this setting may be appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than frequency dependent loss. 01 fully adaptive equalization. the zero position is determined by the selected operating rate, and the low frequency gain of the equalizer is determined algorithmically by analyzing the data patterns and transition positions in the received data. this setting should be used for most applications. 10 precursor equalization analysis. the data patterns and transition positions in the received data are analyzed to determine whether the transmit link partner is applying more or less precursor equalization than necessary. 11 postcursor equalization analysis. the data patterns and transition positions in the received data are analyzed to determine whether the transmit link partner is applying more or less post-cursor equalization than necessary.
29 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table 6. receiver equalization configuration (continued) eq effect [2] 0 default 1 boost. equalizer gain boosted by 6 db, with a 20% reduction in bandwidth, and an increase of 5mw power consumption. may improve performance over long links. table 7. receiver equalizer hold eqhold effect 0 equalizer adaption enabled. the equalizer adaption and analysis algorithm is enabled. this should be the default state. 1 equalizer adaption held. the equalizer is held in its current state. additionally, the adaption and analysis algorithm is reset. table 8. relationship between lane rate and serdes pll output frequency eqboost gain boost (db) bandwidth change (%) power increase (mw) 00 0 0 0 01 2 -30 0 01 4 10 5 11 6 -20 5 when eq is set to 010 or 011, the equalizer is reconfigured to provide analytical data about the amount of pre and post cursor equalization respectively present in the received signal. this can in turn be used to adjust the equalization settings of the transmitting link partner, where a suitable mechanism for communicating this data back to the transmitter exists. status information is provided by setting field dtest in register dtest ( 8.5.76 ) to ? 0111 ? for eqover and ? 0110 ? for equnder. the procedure is as follows: 1. enable the equalizer by setting fields eqhld low and eq to ? 001 ? (register srds_cfg1 8.5.86 ). allow sufficient time for the equalizer to adapt; 2. set eqhld to 1 to lock the equalizer and reset the adaption algorithm. this also causes both eqover and equnder to become low; 3. wait at least 48 ui, and proportionately longer if the cdr activity is less than 100%, to ensure the 1 on eqhld is sampled and acted upon; 4. set eq to ? 010 ? or ? 011 ? , and eqhld to 0. the equalization characteristics of the received signal are analysed (the equalizer response will continue to be locked); 5. wait at least 150 10 3 ui to allow time for the analysis to occur, proportionately longer if the cdr activity is less than 100%; 6. examine eqover and equnder for results of analysis ? if eqover is high, it indicates the signal is over equalized; ? if equnder is high, it indicates the signal is under equalized; 7. set eqhld to 1; 8. repeat items 3 ? 7 if required; 9. set eq to ? 001 ? , and eqhld to 0 to exit analysis mode and return to normal adaptive equalization. note when changing eq from one non-zero value to another, eqhld must already be 1. if this is not the case, there is a chance the equalizer could be reset by a transitory input state (i.e., if eq is momentarily 000). eqhld can be set to 0 at the same time as eq is changed. as the equalizer adaption algorithm is designed to equalize the post cursor, eqover or equnder will only be set during post cursor analysis if the amount of post cursor equalization required is more or less than the adaptive equalizer can provide.
30 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.5 jesd204b descrambler the descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x 14 + x 15 . from the jesd204b specification, the scrambling/descrambling process only occurs on the user data, not on the code group synchronization or the ila sequence. each multi-duc has a separate descrambler that can be enabled independently. the descrambler is enabled by field scr in the multi-duc paged register jesd_n_hd_scr ( 8.5.49 ). 8.3.6 jesd204b frame assembly the dac38rfxx may be programmed as a single or dual dac device, with one jesd rx block designated for each dac. the two jesd rx blocks can be programmed to operate as two separate links or as a single link. the jesd204b defines the following parameters: ? l is the number of lanes ? m is the number of i or q streams per device (2 = 1 iq pair, 4 = 2 iq pairs, 8 = 4 iq pairs) ? f is the number of octets per frame clock period ? s is the number of samples per frame ? hd is the high-density bit which controls whether a sample may be divided over more lanes ? n = nprime is the number of bits per sample (12 or 16 - bits) fields k and l are found in multi-duc paged register jesd_k_l ( 8.5.46 ), m and s in multi-duc paged register jesd_m_s ( 8.5.48 ), and n, nprime and hd in multi-duc paged register jesd_n_hd_scr ( 8.5.49 ). table 9 lists the available jesd204b formats, interpolation rates and sample rate limits for the dac38rfxx. the ranges are limited by the serdes pll vco frequency range, the serdes pll reference clock range, the maximum serdes line rate, and the maximum dac sample frequency. table 10 through table 22 lists the frame formats for each mode. in the frame format tables, i ch (n) [x:y] and q ch (n) [x:y] are bits x through y of the i and q samples at time n of duc channel ch. if [x..y] is not listed, the full sample is assumed. for example, i0(0)[15:8] are bits 15 ? 8 of the i sample at time 0 of duc #0, and q1(1) is the full q sample at time 1 of duc #1. table 9. jesd204b formats for dac38rfxx l-m-f-s-hd 1 tx l-m-f-s- hd 2 tx frame format input resolutio n iq pairs per dac interp input rate max (msps) f dac max (msps) dac38rf86, dac38rf87 dac38rf96, dac38rf97 82121 na 1 tx: table 10 16 1 6 1250 7500 x 16 1 8 1125 9000 x 16 1 12 750 9000 x x 16 1 16 562.5 9000 x x 42111 84111 1 tx: table 11 2 tx: table 12 16 1 6 1250 7500 x 16 1 8 1125 9000 x 16 1 10 900 9000 x 16 1 12 750 9000 x x 16 1 16 562.5 9000 x x 16 1 18 500 9000 x x 16 1 24 375 9000 x x 22210 44210 1 tx: table 13 2 tx: table 14 16 1 8 625 5000 x 16 1 12 625 7500 x x 16 1 16 562.5 9000 x x 16 1 18 500 9000 x x 16 1 20 450 9000 x x 16 1 24 375 9000 x x
31 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated l-m-f-s-hd 1 tx l-m-f-s- hd 2 tx frame format input resolutio n iq pairs per dac interp input rate max (msps) f dac max (msps) dac38rf86, dac38rf87 dac38rf96, dac38rf97 12410 24410 1 tx: table 15 2 tx: table 16 16 1 16 312.5 5000 x x 16 1 24 312.5 7500 x x 44210 88210 1 tx: table 17 2 tx: table 18 16 2 8 625 5000 x 16 2 12 625 7500 x 16 2 16 562.5 9000 x 16 2 24 375 9000 x 24410 48410 1 tx: table 19 2 tx: table 20 16 2 16 312.5 5000 x 16 2 24 312.5 7500 x 24310 48310 1 tx: table 21 2 tx: table 22 12 2 24 375 9000 x table 10. jesd204b frame format for lmfshd = 82121 # un bits 4 8 # en bits 5 10 nibble 1 2 lane rx0 i0[15:8] lane rx1 i0[7:0] lane rx2 i1[15:8] lane rx3 i1[7:0] lane rx4 q0[15:8] lane rx5 q0[7:0] lane rx6 q1[15:8] lane rx7 q1[7:0] table 11. jesd204b frame format for lmfshd = 42111 # un bits 4 8 # en bits 5 10 nibble 1 2 lane rx0 i0[15:8] lane rx1 i0[7:0] lane rx2 q0[15:8] lane rx3 q0[7:0] table 12. jesd204b frame format for lmfshd = 84111 # un bits 4 8 # en bits 5 10 nibble 1 2 lane rx0 i0[15:8] lane rx1 i0[7:0] lane rx2 q0[15:8] lane rx3 q0[7:0] lane rx4 i1[15:8] lane rx5 i1[7:0] lane rx6 q1[15:8]
32 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table 12. jesd204b frame format for lmfshd = 84111 (continued) lane rx7 q1[7:0] table 13. jesd204b frame format for lmfshd = 22210 # un bits 4 8 12 16 # en bits 5 10 15 20 nibble 1 2 3 4 lane rx0 i0 lane rx1 q0 table 14. jesd204b frame format for lmfshd = 44210 # un bits 4 8 12 16 # en bits 5 10 15 20 nibble 1 2 3 4 lane rx0 i0 lane rx1 q0 lane rx2 i1 lane rx3 q1 table 15. jesd204b frame format for lmfshd = 12410 # un bits 4 8 12 16 20 24 28 32 # en bits 5 10 15 20 25 30 35 40 nibble 1 2 3 4 5 6 7 8 lane rx0 i0 q0 table 16. jesd204b frame format for lmfshd = 24410 # un bits 4 8 12 16 20 24 28 32 # en bits 5 10 15 20 25 30 35 40 nibble 1 2 3 4 5 6 7 8 lane rx0 i0 q0 lane rx1 i1 q1 table 17. jesd204b frame format for lmfshd = 44210 # un bits 4 8 12 16 # en bits 5 10 15 20 nibble 1 2 3 4 lane rx0 i0 lane rx1 q0 lane rx2 i1 lane rx3 q1 table 18. jesd204b frame format for lmfshd = 88210 # un bits 4 8 12 16 # en bits 5 10 15 20 nibble 1 2 3 4 lane rx0 i0 lane rx1 q0 lane rx2 i1 lane rx3 q1
33 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table 18. jesd204b frame format for lmfshd = 88210 (continued) lane rx4 i2 lane rx5 q2 lane rx6 i3 lane rx7 q3 table 19. jesd204b frame format for lmfshd = 24410 # un bits 4 8 12 16 20 24 28 32 # en bits 5 10 15 20 25 30 35 40 nibble 1 2 3 4 5 6 7 8 lane rx0 i0 q0 lane rx1 i1 q1 table 20. jesd204b frame format for lmfshd = 48410 # un bits 4 8 12 16 20 24 28 32 # en bits 5 10 15 20 25 30 35 40 nibble 1 2 3 4 5 6 7 8 lane rx0 i0 q0 lane rx1 i1 q1 lane rx2 i2 q2 lane rx3 i3 q3 table 21. jesd204b frame format for lmfshd = 24310 # un bits 4 8 12 16 20 24 # en bits 5 10 15 20 25 30 nibble 1 2 3 4 5 6 lane rx0 i0 q0 lane rx1 i1 q1 table 22. jesd204b frame format for lmfshd = 48310 # un bits 4 8 12 16 20 24 # en bits 5 10 15 20 25 30 nibble 1 2 3 4 5 6 lane rx0 i0 q0 lane rx1 i1 q1 lane rx2 i2 q2 lane rx3 i3 q3
34 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.7 sync interface the dac38rfxx jesd204b interface has two differential sync outputs called sync0 and sync1 to support one or two links. alternatively, gpo0 and gpo1 can be used to output sync as a single-ended cmos level. each of the differential or cmos outputs is enabled by a 2-bit register (fields gpo0_sel, gpo1_sel, sync0b_sel, sync1b_sel in register io_config 8.5.2 ), with bit 0 enabling multi-duc1 sync and bit 1 enabling multi-duc2 sync. if both are enabled, the sync\ signals are or ? ed. the sync signal can be asserted low by the receiver either to make a synchronization request to initialize/reinitialize the link or to report an error to the transmitter. synchronization requests must have a minimum duration of five frames plus nine octets rounded up to the nearest whole number of frames. to report an error, the sync signal is asserted for exactly two frames. the transmitter interprets any negative edge of its sync input as an error and any sync assertion lasting four frames or longer as a synchronization request. see the following sections in the standard for more details. ? 7.6.3 errors requiring re-initialization ? 7.6.4 error reporting via sync interface ? 8.4 sync signal decoding 8.3.8 single or dual link configuration the dac38rfxx jesd204b interface can be configures with one or two links. the advantage of using two links, one for each dac, is that one link can be re-established without affecting the other link and dac. the configuration for each mode of operation are: 1. dual dac, dual link ( a) program fields octetpath0_sel to octetpath7_sel in multi-duc paged registers jesd_crossbar1 ( 8.5.57 ) and jesd_crossbar2 ( 8.5.58 ) so that each multi-duc will pick data off of the appropriate serdes lane. ( b) appropriate bits in field lane_ena in multi-duc paged register jesd_ln_en ( 8.5.45 ) must be set for each multi-duc enable the lanes used. ( c) field one_dac_only in register reset_config ( 8.5.1 ) should be ? 0 ? (default). 2. dual dac, single link ( a) program octetpath0_sel to octetpath7_sel in multi-duc paged registers jesd_crossbar1 ( 8.5.57 ) and jesd_crossbar2 ( 8.5.58 ) so that each multi-duc will pick data off the appropriate serdes lane. ( b) appropriate bits in field lane_ena in multi-duc paged register jesd_ln_en ( 8.5.45 ) must be set for each multi-duc enable the lanes used. ( c) set field one_link_only to ? 1 ? to configure txenable output. 3. single dac, single link ( a) set field one_dac_only in register reset_config ( 8.5.1 ) to ? 1 ? to gate clocks to unused multi- duc2 for power savings. ( b) one_link_only bit does not matter in this case.
35 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.9 multi-device synchronization in many applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that the latency across the link is deterministic and multiple dac devices are completely synchronized such that their outputs are phase aligned. the dac38rfxx achieves the deterministic latency using sysref (jesd204b subclass 1). sysref is generated from the same clock domain as dacclk. after having resynchronized its local multiframe clock (lmfc) to sysref, the dac will request a link re-initialization via sync interface. processing of the signal on the sysref input can be enabled and disabled via the spi interface. the sysref capture circuit and the timing requirements relative to device clock are described in sysref capture circuit . 8.3.10 sysref capture circuit the jesd204b standard for device subclass 1 introduces a sysref signal that can be used as a global timing reference to align the phase of the internal local multiframe clock (lmfc) and frame clock across multiple devices. this allows the system to achieve deterministic latency and align data samples across several data converters. the sysref signal accomplishes this goal by identifying a device clock edge for each chip that can be used as an alignment reference. in particular, the lmfc and frame clock align to the device clock edge upon which the sysref transition from ? 0 ? to ? 1 ? is sampled. sysref may be periodic, one-shot, or ? gapped ? periodic and its period must be a multiple of the lmfc period. figure 29. sysref signal timing with high-speed device clocks, the phase of the sysref signals relative to the device clock must meet the setup/hold time requirements of each individual device clock. historically, this has been done by controlling the board-level routing delay and/or employing commercial clock distribution capable of generating device clocks and sysref signals with programmable delays and with the option of splitting sysref into multiple sysrefs, each with its own fine-tuned delay. since the dac38rfxx family supports device clock frequencies up to 9 ghz, a sysref capture circuit is includes in the dac38rfxx that allows a relaxation in meeting the device clock setup and hold. the sysref capture circuit provides: ? tolerance to manufacturing and environmental variations in sysref phase ? immunity to sampling errors due to setup/hold/meta-stability ? information about phase of sysref relative to dac clock inside the data converter ? software compensation for phase misalignment due to pcb design errors the concepts behind the sysref capture scheme are illustrated in figure 30 .
36 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 30. sysref capture strategy and phase tolerance windows to understand figure 30 , to begin with we ? ll ignore the sysref phase tolerance windows in the lower portion of the figure and focus on the blue clock waveform at the top of the figure. this waveform represents the device clock input to a particular dac chip. the green arrows, labeled ? r ? and ? f ? , correspond to the rising and falling edges of this clock (ignoring for the moment the additional arrows labeled ? er ? and "ef ? ). lower frequency devices captured sysref only on the rising edge of the device clock, the new scheme samples sysref on the falling edge as well, which provides more flexibility when optimizing the setup and hold time of the sysref capture path. moreover, each time a rising sysref edge is captured, the chip remembers the clock phase during which the event occurred, and the system designer can later read back the phase information to observe the sysref timing relative to the device clock at the internal capture point. if sysref transitions close to the rising or falling clock edge sampling points the capture flop setup and hold time may not be met and the observed phase may be unreliable and subject to meta-stability phenomenon. to reduce the sensitivity to setup/hold/meta-stability concerns an ? early ? version of the device clock is generated within the dac and additional sysref samples are taken at the ? early falling ? and ? early rising ? edges of the clock (labeled ? ef ? and ? er ? , respectively, in figure 30 ). the resulting set of four samples is used to narrow down the timing of the rising sysref edge to one of four possible clock phases. if the rising sysref transition takes place between the ? ef ? and ? f ? samples, then sysref is said to occur in phase 1. similarly, if it takes place between the ? f ? and ? er ? samples, then it is said to occur in phase 2. if sysref transitions between the ? er ? and ? r ? samples, then it is said to occur in phase 3. and, finally, if the sysref rising edge event happens between the ? r ? and ? ef ? samples, then it is said to occur in phase 4. as mentioned before, the chip remembers all observed sysref phases and the user can later read them back. since the delay between ? early ? and ? on time ? versions of the clock is intentionally chosen to be larger than the setup/hold/meta-stability window, at most one of the four samples can be affected even when the sysref transitions right at one of the four sampling points. thus, the uncertainty in the observed sysref timing is limited to adjacent phases, and with twice as many sampling phases the resolution of the timing information is improved by a factor of two. referring to the lower portion of figure 30 , the user can now see how this information regarding the observed sysref phases is used to devise a reliable sysref capture methodology with a high degree of tolerance to manufacturing and environmental variations in sysref phase. based on the sysref phases observed for a particular dac chip during system characterization, the system designer can select one of four so-called ? phase tolerance window ? options (denoted ? ? 00 ? , ? 01 ? , ? 10 ? , and ? 11 ? ) to maximize immunity to manufacturing and environmental variations. for example, consider the default phase tolerance window labeled ? window=00 ? in the figure. if, during characterization, the system designer observes (by reading back the recorded phase observations) that the rising sysref edge nominally occurs in either 1 or 2 or both (i.e. 12) then he would program that particular dac chip to use phase tolerance window ? 00 ? . this mapping is indicated in the figure with the label ? 1| 12| 2: window=00 ? . having programmed the device to use window ? 00 ? , all future sysref events that occur in 1 or 2 would trigger the lmfc and frame clock to be aligned using the following rising clock edge as the alignment reference (as indicated by the red arrow pointing to rising clock edge ? r ? and labeled ? window=00/01 alignment edge ? ).
37 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated the full extent of each phase tolerance window is indicated in the figure using ? box and whisker ? plots. for the ? window=00 ? example, the ? box ? portion of the plot indicates that the phase tolerance window is centered on 12 (to be precise on the boundary between 1 and 2) and the ? whisker ? portion indicates that even if the rising edge of sysref occurs as early as the preceding 4 or as late as the following 3 it still results in lmfc and frame clock alignment to the same rising clock edge indicated by the red arrow labeled ? window=00/01 alignment edge ? . when programmed for phase tolerance window ? 00 ? , the dac chip is tolerant to variations in the sysref timing ranging from a rising sysref edge that occurs just after one rising edge of clock to just before the next rising edge of the clock. the qualifying phrases ? just after ? and ? just before ? are used here to indicate that the sysref transition must occur far enough away from the rising edges of the clock to avoid setup/hold violations and prevent the device from concluding that the sysref transition has crossed out off the phase tolerance window when in fact it has not. the tolerance range for window ? 00 ? is from rising clock edge to rising clock edge and is indicated in the figure by the green text labeled ? tolerance = r ? r ? . following the above example, if characterization reveals sysref timing centered on 23 then phase tolerance window ? 01 ? (with tolerance for sysref rising edge events from ef to ef) should be chosen. notice that this option is tolerant even to rising sysref edges that occur after the rising device clock edge (i.e. in 4) and will treat them just as if they had occurred in one of the earlier three phases, aligning to the same rising device clock edge indicated by the red arrow labeled ? window=00/01 alignment edge ? . this allows the system designer to tolerate pcb design errors and/or environmental and manufacturing variations ? achieving his intended alignment without having to make physical changes to the board to adjust the sysref timing. similarly, if characterization indicates that sysref timing is centered on 34 or 41 then phase tolerance window ? 10 ? or ? 11 ? can be selected, resulting in tolerance for ? f ? f ? or ? er ? er ? sysref timing, respectively. note, however, that in these two cases the alignment reference edge is by default taken to be the subsequent rising edge of the device clock. since this may not be the desired behavior, the dac38rfxx allows the user to program in an optional alignment offset of 1 if the default offset of 0 does not achieve the desired alignment. this feature is illustrated in figure 31 where the user can see that by setting the alignment offset to -1, phase tolerance windows ? 10 ? and ? 11 ? can be made to trigger alignment to the earlier rising device clock edge used by windows ? 00 ? and ? 01 ? . alternatively, the window ? 00 ? and ? 01 ? alignment edge can be pushed one cycle later by setting their alignment offset to +1. figure 31. optional sysref alignment offset several important controls related to sysref alignment and capture timing are contained in register sysr_capture ( 8.5.78 ). for example, as mentioned before, the device is capable of monitoring the observed phases of the rising sysref edge events; however, in order to avoid unwanted noise coupling from the sysref circuits into the dac output, the sysref monitoring circuits are disabled by default. field sysr_status_ena enables sysref status monitoring. field sysr_phase_wdw contains the the phase tolerance window selected for normal operation, which is optimized during characterization. field sysr_align_dly contains the control that allows the system designer to optionally offset the sysref alignment event by 1 device clock cycles. field sysr_status_ena enables the sysref capture alignment accumulation and will generate alarms when enabled. writing a ? 1 ? to field sysr_align_sync clears the accumulated sysref alignment statistics. the sysref alignment block can be bypassed completely by field sysref_bypass_align, in which case sysref is latched by the rising edge of dacclk.
38 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated when field sysr_status_ena is high the device records the phase associated with each sysref event for use in characterizing the sysref capture timing and selecting an appropriate phase tolerance window. the phase data is available in two forms. first, each of the four phases has a corresponding ? sticky ? alarm flag indicating which phases have been observed since the last time the register was cleared. in addition, the device also accumulates statistics on the relative number of occurrences of each phase spanning multiple sysref events using saturating 8-bit counters. these accumulated real-time sysref statistics allow us to account for time-varying effects during characterization such as potential timing differences between the 1st and nth edges in a ? gapped ? sysref pulse train. the counters are fields phase1_cnt and phase2_cnt in register sysref12_cnt ( 8.5.10 ), phase3_cnt and phase4_cnt in register sysref34_cnt ( 8.5.11 ), and align_to_r1_cnt and align_to_r3_cnt in register sysref_align_r ( 8.5.9 ). the accumulated sysref statistics can be cleared by writing ? 1 ? to sysr_align_sync. this sync signal affects only the sysref statistics monitors and does not cause a sync of any other portions of the design. before collecting phase statistics, the user must first enable the sysref status monitoring logic by setting the sysr_status_ena bit. the user must then generate a repeating sysref input before using sysr_align_sync to clear the statistic counters. this is necessary to flush invalid data out of the status pipeline. the ? sticky ? alarm flags indicating which of the four phases have been observed since the last sysr_align_sync write of ? 1 ? are fields alm_sysrphase1 to alm_sysrphase4 and are contained in the alm_sysref_det register ( 8.5.6 ). 8.3.11 jesd204b subclass 0 support some functionality has been implemented to support subclass 0 operation. note that programming the subclassv configuration parameter has no functional impact on the logic. the value programmed for subclassv is only used in the initial lane alignment (ila) sequence. the following configuration parameters are used to support subclass 0 operation: ? field sysref_mode in register jesd_sysr_mode ( 8.5.56 ) = 0 ? field disable_err_rpt in register jesd_err_out ( 8.5.53 ) = 1 ? field min_latency_ena in register jesd_match ( 8.5.50 ) = 1 8.3.12 serdes test modes through serial programming the dac38rfxx supports a number of basic pattern generation and verification of serdes via the serial interface. three pseudo random bit stream (prbs) sequences are available, along with an alternating 0/1 pattern and a 20-bit user-defined sequence. the 2 7 - 1, 2 31 - 1 or 2 23 ? 1 sequences implemented can often be found programmed into standard test equipment, such as a bit error rate tester (bert). pattern generation and verification selection is via field testpatt in register srds_cfg1 ( 8.5.86 ), as shown in table 23 . table 23. serdes test pattern selection testpatt effect 000 test mode disabled. 001 alternating 0/1 pattern. an alternating 0/1 pattern with a period of 2 ui. 010 verify 2 7 - 1 prbs. uses a 7-bit lfsr with feedback polynomial x 7 + x 6 + 1. 011 verify 2 23 - 1 prbs. uses an itu o.150 conformant 23-bit lfsr with feedback polynomial x 23 + x 18 + 1. 100 verify 2 31 - 1 prbs. uses an itu o.150 conformant 31-bit lfsr with feedback polynomial x 31 + x 28 + 1. 101 user-defined 20-bit pattern. uses the usr patt ieee1500 tuning instruction field to specify the pattern. the default value is 0x66666. 11x reserved. pattern verification compares the output of the serial to parallel converter with an expected pattern. when there is a mismatch, the testfail bit is driven high, which can be programmed to come out the alarm terminal by setting field dtest in register dtest ( 8.5.76 ) to ? 0011 ? .
39 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.13 serdes test modes through ieee 1500 programming dac38rfxx also provide a number of advanced diagnostic capabilities controlled by the ieee 1500 interface. these are: ? accumulation of pattern verification errors; ? the ability to map out the width and height of the receive eye, known as eye scan; ? rreal-time monitoring of internal voltages and currents; the serdes blocks support the following ieee1500 instructions: table 24. ieee1500 instruction for serdes receivers instruction opcode description ws_bypass 0x00 bypass. selects a 1-bit bypass data register. use when accessing other macros on the same ieee1500 scan chain. ws_cfg 0x35 configuration. write protection options for other instructions. ws_core 0x30 core. fields also accessible via dedicated core-side ports. ws_tuning 0x31 tuning. fields for fine tuning macro performance. ws_debug 0x32 debug. fields for advanced control, manufacturing test, silicon characterization and debug. ws_unshadowed 0x34 unshadowed. fields for silicon characterization. ws_char 0x33 char. fields used for eye scan. the data for each serdes instruction is formed by chaining together sub-components called head, body (receiver or transmitter) and tail. dac38rfxx uses two serdes receiver blocks r0 and r1, each of which contains 4 receive lanes (channels), the data for each ieee1500 instruction is formed by chaining {head, receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. a description of bits in head, body and tail for each instruction is given as follows: note all multi-bit signals in each chain are packed with bits reversed e.g. mpy[7:0] in ws_core head subchain is packed as {retime, enpll, mpy[0:7], vrange, lb[0:1]}. all data register reads from serdes block r0 should read 1 bit more than the desired number of bits and discard the first bit received on tdo e.g., to read 40-bit data from r0 block, 41 bits should be read off from tdo and the first bit received should be discarded. similarly, any data written to serdes block r0 data registers should be prefixed with an extra 0. table 25. ws_cfg chain field description head (starting from the msb of chain) retime no function. core_we core chain write enable. receiver (for each lane 0, 1, 2, 3) core_we core chain write enable. tuning_we tuning chain write enable. debug_we reserved. char_we char chain write enable. unshadowed_we reserved. tail (ending with the lsb of chain) core_we core chain write enable. tuning_we tuning chain write enable. debug_we reserved. retime no function. chain length = 26 bits
40 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table 26. ws_core chain field description head (starting from the msb of chain) retime no function. enpll pll enable. mpy[7:0] pll multiply. vrange vco range. endivclk enable divclk output lb[1:0] loop bandwidth receiver (for each lane 0,1,2,3) enrx receiver enable. sleeprx receiver sleep mode. buswidth[2:0] bus width. rate[1:0] operating rate. invpair invert polarity. term[2:0] termination. align[1:0] symbol alignment. los[2:0] loss of signal enable. cdr[2:0] clock/data recovery. eq[2:0] equalizer. eqhld equalizer hold. enoc offset compensation. loopback[1:0] loopback. bsinrxp boundary scan initialization. bsinrxn boundary scan initialization. reserved reserved. testpatt[2:0] test pattern selection. testfail test failure (real time). lostdtct loss of signal detected (real time). bsrxp boundary scan data. bsrxn boundary scan data. ocip offset compensation in progress. eqover receiver signal over equalized. equnder receiver signal under equalized. lostdtct loss of signal detected (sticky). sync re-alignment done, or aligned comma output (sticky). retime no function. tail (ending with the lsb chain) clkbyp[1:0] clock bypass. sleeppll pll sleep mode. reserved reserved. lock pll lock (real time). bsinitclk boundary scan initialization clock. enbstx enable tx boundary scan. enbsrx enable rx boundary scan. enbspt rx pulse boundary scan. reserved reserved. nearlock pll near to lock. unlock pll lock (sticky).
41 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table 26. ws_core chain (continued) field description cfg ovr configuration over-ride. retime no function. chain length = 196 bits table 27. ws_tuning chain field description head (starting from the msb of chain) retime no function. receiver (for each lane 0,1,2,3) patterrthr[2:0] resync error threshold. patt timer prbs timer. rxdsel[3:0] status select. encor enable clear-on-read for error counter. eqzero[4:0] eqz ovri equalizer zero. eqz ovr equalizer zero over-ride. eqlevel[15:0] eq ovri equalizer gain observe or set. eq ovr equalizer over-ride. eqboost[1:0] equalizer gain boost. rxasel[2:0] selects amux output. tail (ending with the lsb chain) asel[3:0] selects amux output. usr patt[19:0] user-defined test pattern. retime no function. chain length = 174 bits table 28. ws_char chain field description head (starting from the msb of chain) retime no function. receiver (for each lane 0,1,2,3) testfail test failure (sticky). ecount[11:0] error counter. esword[7:0] eye scan word masking. es[3:0] eye scan. espo[6:0] eye scan phase offset. es bit select[4:0] eye scan compare bit select. esvo[5:0] eye scan voltage offset. esvo ovr eye scan voltage offset override. eslen[1:0] eye scan run length. esrun eye scan run. esdone eye scan done. tail (ending with the lsb chain) retime no function. chain length = 194 bits
42 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.14 error counter all receive channels include a 12-bit counter for accumulating pattern verification errors. this counter is accessible via the ecount ieee1500 char field. it is an essential part of the eye scan capability (see the eye scan section). the counter increments once for every cycle that the testfail bit is detected. the counter does not increment when at its maximum value (i.e., all 1s). when an ieee1500 capture is performed, the count value is loaded into the ecount scan elements (so that it can be scanned out), and the counter is then reset, provided ncor is set high. ecount can be used to get a measure of the bit error rate. however, as the error rate increases, it becomes less accurate due to limitations of the pattern verification capabilities. specifically, the pattern verifier checks multiple bits in parallel (as determined by the rx bus width), and it is not possible to distinguish between 1 or more errors. 8.3.15 eye scan all receive channels provide features which facilitate mapping the received data eye or extracting a symbol response. a number of fields accessible via the ieee1500 char scan chain allow the required low level data to be gathered. the process of transforming this data into a map of the eye or a symbol response must then be performed externally, typically in software. the basic principle used is as follows: ? enable dedicated eye scan input samplers, and generate an error when the value sampled differs from the normal data sample; ? apply a voltage offset to the dedicated eye scan input samplers, to effectively reduce their sensitivity; ? apply a phase offset to adjust the point in the eye that the dedicated eye scan data samples are taken; ? reset the error counter to remove any false errors accumulated as a result of the voltage or phase offset adjustments; ? run in this state for a period of time, periodically checking to see if any errors have occurred; ? change voltage and/or phase offset, and repeat. alternatively, the algorithm can be configured to optimize the voltage offset at a specified phase offset, over a specified time interval. eye scan can be used in both synchronous and asynchronous systems, while receiving normal data traffic. the ieee1500 char fields used to directly control eye scan and symbol response extraction are es, esword, es bit select, eslen, espo, esvo, esvo ovr, esrun and esdone. eye scan errors are accumulated in ecount. the required eyescan mode is selected via the es field, as shown in table 29 . when enabled, only data from the bit position within the 20-bit word specified via es bit select is analyzed. in other words, only eye scan errors associated with data output at this bit position will accumulate in ecount. the maximum legal es bit select is 10011. table 29. eye scan mode selection es[3:0] effect 0000 disabled. eye scan is disabled. 0x01 compare. counts mismatches between the normal sample and the eye scan sample if es[2] = 0, and matches otherwise. 0x10 compare zeros. as es = 0x01, but only analyses zeros, and ignores ones. 0x11 compare ones. as es = 0x01, but only analyses ones, and ignores zeroes. 0100 count ones. increments ecount when the eye scan sample is a 1. 1x00 average. adjusts esvo to the average eye opening over the time interval specified by eslen. analyses zeroes when es[2] = 0, and ones when es[2]= 1. 1001 1110 outer. adjusts esvo to the outer eye opening (i.e. lowest voltage zero, highest voltage 1) over the time interval specified by eslen. 1001 analyses zeroes, 1110 analyses ones. 1010 1101 inner. adjusts esvo to the inner eye opening (i.e. highest voltage zero, lowest voltage 1) over the time interval specified by eslen. 1010 analyses zeroes, 1101 analyses ones.
43 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table 29. eye scan mode selection (continued) es[3:0] effect 1x11 timed compare. as es = 001x, but analyses over the time interval specified by eslen. analyses zeroes when es[2] = 0, and ones when es[2] = 1. when es[3] = 0, the selected analysis runs continuously. however, when es[3] = 1, only the number of qualified samples specified by esled, as shown in table 30 . in this case, analysis is started by writing a 1 to esrun (it is not necessary to set it back to 0). when analysis completes, esdone is set to 1. table 30. eye scan run length eslen number of samples analyzed 00 127 01 1023 10 8095 11 65535 when esvo ovr = 1, the esvo field determines the amount of offset voltage that is applied to the eye scan data samplers associated with rxpi and rxni. the amount of offset is variable between 0 and 300 mv in increments of ~10 mv, as shown table 31 . when es[3] = 1, esvo ovr must be 0 to allow the optimized voltage offset to be read back via esvo. table 31. eye scan voltage offset esvo offset (mv) 100000 -310 ? ? 111110 -20 111111 -10 000000 0 000001 10 000010 20 ? ? 011111 300 the phase position of the samplers associated with rxpi and rxni, is controlled to a precision of 1/32ui. when es is not 00, the phase position can be adjusted forwards or backwards by more than one ui using the espo field, as shown in table 32 . in normal use, the range should be limited to 0.5 ui (+15 to ? 16 phase steps). table 32. eye scan phase offset espo offset (1/32 ui) 011111 +63 ? ? 000001 +1 000000 0 111111 -1 ? ? 100000 -64
44 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.16 jesd204b pattern test the dac38rfxx supports the following test patterns for jesd204b: ? link layer test pattern by setting field jesd_test_seq in register jesd_ln_en ( 8.5.45 ) and monitoring the lane alarms (1 = fail, 0 = pass) ? verify repeating /d.21.5/ high frequency pattern for random jitter (rj) ? verify repeating /k.28.5/ mixed frequency pattern for deterministic jitter (dj) ? verify repeating initial lane alignment (ila) sequence ? rpat, jspat or jtspat pattern can be verified using errors counter of 8b/10b errors produced over an amount of time to get an estimate of ber. ? transport layer test pattern: implements a short transport layer pattern check based on f = 1, 2, 4 or 8. the short test pattern has a duration of one frame period and is repeated continuously for the duration of the test. each sample has a unique value that can be identified with the position of the sample in the user data format. the sample values are such that correct sample values will never be decoded at the receiver if there is a mismatch between the mapping formats being used at the transmitter and receiver devices. this can generally be accomplished by ensuring there are no repeating sub patterns within the stream of samples being transmitted. refer to the jesd204b standard section 5.1.6 for more details.
45 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated the dac38rfxx expects the test samples, in a frame, transmitted by an logic device as per table 33 : table 33. short test patterns jesd mode i0 q0 i1 q1 82121 7cb8, f431, 6da9, e520 7cb8, f431, 6da9, e520 n/a n/a 42111 7cb8, f431 6da9, e520 f871, e962 da53, cb40 22210 7cb8 6da9 n/a n/a 12410 7cb8 6da9 n/a n/a 44210 7cb8 6da9 7cb8 6da9 24410 7cb8 6da9 7cb8 6da9 41121 7cb8, f431, 6da9, e520 81180 7c00, b800, f400, 3100, 6d00, a900, e500, 2000, f800, 7100, e900, 6200, da00, 5300, cb00, 4000 n/a n/a n/a 24310 87c0, f4b0 d310, a960 0e50, f820 9710, 62e0 41380 87c0, f4b0, d310, a960, 0e50, f820, 9710, 62e0 n/a n/a n/a the short test pattern has duration of one frame period and is repeated continuously for the duration of the test. each sample has a unique value that can be identified with the position of the sample in the user data format. the sample values are such that correct sample values will never be decoded at the receiver if there is a mismatch between the mapping formats being used at the transmitter and receiver devices. this can generally be accomplished by ensuring there are no repeating sub patterns within the stream of samples being transmitted. following are the steps required to execute the short test functionality in dac38rfxx. 1. configure other registers, make sure clocks are up and running. 2. start driving short test patterns 3. clear short test alarm by writing ? 0 ? to field alm_from_shorttest in register alm_sysref_pap ( 8.5.67 ). this is a paged register, one for each multi-duc. 4. enable short test by writing a ? 1 ? to field shorttest_ena in register multiduc_cfg2 ( 8.5.14 ). 5. read the short test alarm from field alm_from_shorttest in register alm_sysref_pap ( 8.5.67 ). this is a paged register, one for each multi-duc if the alarm read from the register is high, the short test has detected an error. 8.3.17 multiband duc (multi-duc) each dac output in the dac38rfxx is supported by a dual band digital upconverter (duc), which is called a multi-duc. figure 32 shows the signal processing features of each of the two multi-ducs. the two paths are identical and independent. the spi interface registers for the multi-ducs are addressed through paging, with page 0 supporting multi-duc1 and page 1 supporting multi-duc2. register page_set ( 8.5.8 ) is used to set the pages. both pages can be selected at the same time to program both multi-ducs simultaneously with the same settings. each multi-duc has 2 duc channels, called path ab and path cd. the output of one multi-duc can be added to the signal of the other multi-duc to allow a configuration with 4 total ducs summed together for 1 dac. after quadrature modulation is a sin(x)/x compensation filter, followed by the multiband summation block. the multi- band summation block had the ability to add the signals from the other multi-duc for a combined 4 ducs, each with independent frequency control. the final block is an output delay block with 0 ? 15 sample range.
46 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 32. dac38rfxx multi-duc signal processing block diagram 8.3.17.1 multi-duc input each multi-duc, accepts data from up to 8 serdes lanes. a crossbar switch allows any serdes lane to be mapped to any other serdes lane. the crossbar switch is controlled by fields octetpathx_sel (x = [0..7]) in registers jesd_crossbar1 ( 8.5.57 ) and jesd_crossbar2 ( 8.5.58 ). as shown in table 9 , the multiband duc can be configured as either a single duc with 1 iq input, or a dual duc with 2 iq inputs, which is selected by asserting field dual_iq in register multiduc_cfg1 ( 8.5.13 ). 8.3.17.2 interpolation filters the digital upconverter first increases the sample rate of the iq signal from the input sample rate to the final dac sample rate through a series of interpolation filters. different sets of filters are used to achieve different rates, as shown in table 34 . the interpolation rate is selected by field interp in register multiduc_cfg1 ( 8.5.13 ). table 34. fir filters used for different interpolation rates filters used interpolation rate fir0 (2x) fir1 (2x) lpfir0_5x fir2 (2x) lpfir0_3x fir3 (2x) lpfir1_3x 6 x x 8 x x x x 10 x x 12 x x x 16 x x x x 18 x x x 20 x x x 24 x x x x 16 16 complex mixer (fmix or cmix) jesd204b interface 16 16 xn xn xn xn x sin(x) complex mixer (fmix or cmix) 48-bit nco2 cos sin 48-bit nco1 cos sin cmix control (n*fs/4) input mux multiband summation x sin(x) pap gain pap gain pap from 2nd multi-duc delay i q i q path ab path cd
47 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated the fir filter coefficients are shown in table 35 the fir filters are design with a passband bw of 0.4 x f inpu t, a stopband attenuation of 90 dbc and ripple of < 0.001 db. the composite frequency response for each interpolation factor are shown in figure 33 to figure 40 . figure 33. composite magnitude response for 6x interpolation figure 34. composite magnitude response for 8x interpolation figure 35. composite magnitude response for 10x interpolation figure 36. composite magnitude response for 12x interpolation f/fdac magnitude (db) 0 0.075 0.15 0.225 0.3 0.375 0.45 -160 -140 -120 -100 -80 -60 -40 -20 0 20 d003 f/fdac magnitude (db) 0 0.075 0.15 0.225 0.3 0.375 0.45 -160 -140 -120 -100 -80 -60 -40 -20 0 20 d004 f/fdac magnitude (db) 0 0.075 0.15 0.225 0.3 0.375 0.45 -160 -140 -120 -100 -80 -60 -40 -20 0 20 d002_8x f/fdac magnitude (db) 0 0.075 0.15 0.225 0.3 0.375 0.45 -160 -140 -120 -100 -80 -60 -40 -20 0 20 d001
48 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 37. composite magnitude response for 16x interpolation figure 38. composite magnitude response for 18x interpolation figure 39. composite magnitude response for 20x interpolation figure 40. composite magnitude response for 24x interpolation table 35. fir filter coefficients tap fir0 fir1 lpfir0_5x fir2 lpfir0_3x fir3 lpfir1_3x invsinc 1 6 -12 -6 29 -14 3 25 1 2 0 0 -22 0 -61 0 88 -4 3 -19 84 -51 -214 -125 -25 22 13 4 0 0 -89 0 -95 0 -576 -50 5 47 -336 -117 1209 181 150 -1764 592 6 0 0 -106 2048 681 256 -2263 -50 7 -100 1006 -18 1209 972 150 491 13 8 0 0 171 0 347 0 8139 -4 9 192 -2691 449 -214 -1475 -25 18625 1 10 0 0 745 0 -3519 0 26365 11 -342 10141 930 29 -3528 3 26365 12 0 16384 841 707 18625 13 572 10141 338 9337 8139 14 0 0 -618 19445 491 15 -914 -2691 -1892 26299 -2263 16 0 0 -3147 26299 -1764 17 1409 1006 -3872 19445 -576 f/fdac magnitude (db) 0 0.075 0.15 0.225 0.3 0.375 0.45 -160 -140 -120 -100 -80 -60 -40 -20 0 20 d006 f/fdac magnitude (db) 0 0.075 0.15 0.225 0.3 0.375 0.45 -160 -140 -120 -100 -80 -60 -40 -20 0 20 d007 f/fdac magnitude (db) 0 0.075 0.15 0.225 0.3 0.375 0.45 -160 -140 -120 -100 -80 -60 -40 -20 0 20 d001 f/fdac magnitude (db) 0 0.075 0.15 0.225 0.3 0.375 0.45 -160 -140 -120 -100 -80 -60 -40 -20 0 20 d005
49 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated table 35. fir filter coefficients (continued) tap fir0 fir1 lpfir0_5x fir2 lpfir0_3x fir3 lpfir1_3x invsinc 18 0 0 -3500 9337 22 19 -2119 -336 -1564 707 88 20 0 0 2121 -3528 25 21 3152 84 7336 -3519 22 0 0 13430 -1475 23 -4729 -12 19426 347 24 0 24231 972 25 7420 26904 681 26 0 26904 181 27 -13334 24231 -95 28 0 19426 -125 29 41527 13430 -61 30 65536 7336 -14 31 41527 2121 32 0 -1564 33 -13334 -3500 34 0 -3872 35 7420 -3147 36 0 -1892 37 -4729 -618 38 0 338 39 3152 841 40 0 930 41 -2119 745 42 0 449 43 1409 171 44 0 -18 45 -914 -106 46 0 -117 47 572 -89 48 0 -51 49 -342 -22 50 0 -6 51 192 52 0 53 -100 54 0 55 47 56 0 57 -19 58 0 59 6
50 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.17.3 jesd and interpolation programming table 36 lists the register field values required for each jesd and interpolation mode. the register field addresses are listed in table 37 . table 36. register programming for jesd and interpolation mode mode register field programming l-m-f-s-hd 1 tx/2tx interp clkjesd_div interp (4-0) clkjesd _div (3-0) clkjesd _out_di v (3-0) l_m1 (4-0) f_m1 (7-0) m_m1 (7-0) s_m1 (4-0) hd n_m1/n ? _ m1 (4-0) 82121/na 6 div24 00011 0110 0011 00111 0x00 0x01 00001 1 01111 8 div32 00100 0111 0100 12 div48 00110 1010 0110 16 div64 01000 1011 0111 42111/84111 6 div12 00011 0010 0011 00011 0x00 0x01 00000 1 01111 8 div16 00100 0011 0100 10 div20 00101 0101 0101 12 div24 00110 0110 0110 16 div32 01000 0111 0111 18 div36 01001 1001 1000 24 div48 01100 1010 1010 22210/44210 8 div8 00100 0001 0100 00001 0x01 0x01 00000 0 01111 12 div12 00110 0010 0110 16 div16 01000 0011 0111 18 div18 01001 0100 1000 20 div20 01010 0101 1001 24 div24 01100 0110 1010 12410/24410 16 div8 01000 0001 0111 00000 0x03 0x01 00000 0 01111 24 div12 00110 0110 1010 44210/88210 8 div8 00100 0001 0100 00011 0x01 0x03 00000 0 01111 12 div12 00110 0010 0110 16 div16 01000 0011 0111 24 div24 01100 0110 1010 24410/48410 16 div8 01000 0001 0111 00011 0x03 0x03 00000 0 01111 24 div12 01100 0010 1010 24310/48310 24 div16 01100 0011 1010 00011 0x02 0x03 00000 0 01011 table 37. register field addresses for jesd and interpolation programming register field name register register address bit(s) hyperlink interp multiduc_cfg1 0x0a 12-8 8.5.13 clkjesd_div serdes_clk 0x25 15-12 8.5.28 clkjesd_out_div 11-8 l_m1 jesd_k_l 0x4c 4-0 8.5.47 f_m1 jesd_rbd_f 0x4b 7-0 8.5.46 m_m1 jesd_m_s 0x4d 15-8 8.5.48 s_m1 4-0 hd jesd_n_hd_scr 0x4e 6 8.5.49 n_m1 12-8 n_m1 ? (nprime_m1) 4-0 all registers are paged!
51 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.17.4 digital quadrature modulator each duc in the dac38rfxx has digital quadrature modulator (dqm) blocks with independent numerically controlled oscillators (nco) that converts the complex input signal to a real signal with flexible frequency placement between 0 and f dac /2. the ncos are enabled by fields ncoab_ena and ncocd_ena in register multiduc_cfg2 ( 8.5.14 ). the ncos have 48-bit frequency registers (freq_ncoab ( 8.5.25 ) and freq_ncocd ( 8.5.26 )) and 16-bit phase registers (phase_ncoab ( 8.5.23 ) and phase_ncocd ( 8.5.24 )) that generate the sine and cosine terms for the complex mixing. the nco block diagram is shown in figure 41 . figure 41. nco block diagram synchronization of the ncos occurs by resetting the nco accumulators to zero. the synchronization source is selected by fields syncsel_ncoab and syncsel_ncocd in register syncsel1 ( 8.5.29 ). the frequency word in the freq_ncoab and freq_ncocd registers are added to the accumulators every clock cycle, f dac . the frequency and phase offset of the ncos are: (1) (2) treating the complex channels as complex vectors of the form i + j q, the output of the dqm is: (3) (4) where t is the time since the last resetting of the nco accumulator and the fields mixerab_gain and mixercd_gain in register multiduc_cfg2 ( 8.5.13 ) are either 0 or 1. the maximum output amplitude of the dqm occurs if i in (t) and q in (t) are simultaneously full scale amplitude and the sine and cosine arguments are equal to an integer multiple of /4. with mixerab_gain or mixercd_gain = 0, the gain through the dqm is sqrt(2)/2 or -3 db. this loss in signal power is in most cases undesirable, and it is recommended that the gain function be used to increase the signal by 3 db to compensate. with mixerab_gain or mixercd_gain = 1, the gain through the dqm is sqrt(2) or +3 db, which can cause clipping of the signal if i in (t) and q in (t) are simultaneously near full scale amplitude and should therefore be used with caution. 8.3.17.5 low power coarse resolution mixing modes in addition to the nco the dac38rfxx also has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixing frequencies n x f dac /8. using the coarse mixer instead of the full mixers will result in lower power consumption. treating the two complex channels as complex vectors of the form i(t) + j q(t), the outputs of the coarse mixer is equivalent to: ^ ` mixercd gain cd inputcd ncocd cd inputcd ncocd cd output i cos ? i w / 4 vlq ? i w / _ 1 2 2 2 u u u ^ ` mixerab gain ab inputab ncoab ab inputab ncoab ab output i cos ? i w / 4 vlq ? i w / _ 1 2 2 2 u u u ab or cd / ? 16 _ 2 2 u phase ncoab or cd ncoab or cd f 48 _ 2 u dac freq ncoab or cd f frequency register 48 accumulator 48 reset clk f dac nco sync via syncsel_nco(3:0) 48 48 phase register 16 16 16 look up table 16 16 sin cos
52 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated (5) (6) where f cmix_ab and f cmix_cd and the fixed mixing frequency selected by fields cmix_ab or cmix_cd in register cmix ( 8.5.21 ). the coarse mixer blocks are disabled by setting cmix_ab and cmix_cd to 0x0. the nco and coarse mixers can be enabled simultaneously, although this is not useful in most cases as the full frequency range can be covered by the nco. 8.3.17.6 inverse sinc filter the dac38rfxx have a 9-tap inverse sinc filter (invsinc) that runs at the dac update rate (fdac) that can be used to flatten the frequency response of the sample-and-hold output. the dac sample-and-hold output sets the output current and holds it constant for one dac clock cycle until the next sample, resulting in the well known sin(x)/x or sinc(x) frequency response ( figure 42 , red line). the inverse sinc filter response ( figure 42 , blue line) has the opposite frequency response from 0 to 0.4 x f dac , resulting in the combined response ( figure 42 , green line). between 0 to 0.4 x f dac , the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03 db error. the inverse sinc filter has a gain > 1 at all frequencies. therefore, the signal input to invsinc must be reduced from full scale to prevent saturation in the filter. the amount of back-off required depends on the signal frequency, andis set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 db). for example, if the signal input to invsinc is at 0.25 x f dac , the response of invsinc is 0.9 db, and the signal must be backed off from full scale by 0.9 db to avoid saturation. the advantage of invsinc having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based on its frequency. the inverse sinc filters are enabled by fields isfirab_ena and isfircd_ena in register multiduc_cfg1 ( 9.5.9 ). figure 42. composite magnitude spectrum for invsinc 8.3.17.7 summation block for dual duc modes when using the dual duc modes, the outputs of the two aqm blocks are summed together to form a composite signal for the dac output, configured by field outsum_sel in register outsum ( 8.5.22 ). the input signals to the ducs much be scaled such that the signal does not exceed fullscale during summation. this field can also be configures to add the signals from the adjacent multi-duc to enable a four duc signal. 8.3.18 pa protection block the dac38rfxx incorporates an optional power amplifier protection (pap) block to monitor when the input signal is two large, for example when an interface error occurs, and reduces the output signal power of the dac. the pap block achieves the functionality of reducing the input signal that crosses the threshold through three main sub-blocks. these are pap trigger generation block, pap gain state machine and gain block. 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 C4 C3 C2 C1 0 1 2 3 4 f/f dac magnitude (db) g056 sin(x)/x corrected fir4 _ _ 2 2 u u cd inputcd cmix cd inputcd cmix cd output i cos ? i w 4 vlq ? i w _ _ 2 2 u u ab inputab cmix ab inputab cmix ab output i cos ? i w 4 vlq ? i w
53 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated the pap block keeps track of the input signal power by maintaining a sliding window accumulation of last n samples. n is selectable to be 32, 64 or 128 based on the setting ( table 38 ) of fields papab_sel_dly in register pap_cfg_ab ( 8.5.35 ) and papcd_sel_dly in register pap_cfg_cd ( 8.5.36 ). the average amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line (n). the result is then compared against the threshold in fields papab_thresh in register pap_cfg_ab ( 8.5.35 ) and papcd_thresh in register pap_cfg_cd ( 8.5.36 ). if the threshold is violated, gain state machine is triggered which generated gain value to ramp down the dac output signal amplitude. after the input signal returns to normal value, the state machine ramps up the dac output signal amplitude. table 38. pap delay line selection pap_sel_dly[1:0] # of samples averaged 00 32 01 64 10 128 11 reserved the generation of the pap trigger as explained as follows: ? the i and q samples are treated separately ? either can trigger attenuation ? in dual duc modes, each iq pair is treated separately and has a separate gain block ? 8 samples at the input are put through an absolute value circuit (all 2 ? s complement) ? next these values are vector summed to get a 12 bit result ? then 12 bit result is placed into the delay line and summed into the accumulator ? the accumulator is also subtracting out the delayed 12 bit word corresponding to n = 32, n = 64 or n = 128 ? finally the accumulator output is divided down by n and rounded to 13 bits. these 13 bits are compared to the threshold in the spi registers. a pap_trig occurs if the threshold is exceeded. the pap gain state machine generates the pap gain value to be applied on the output stream to reduce the output signal amplitude. the state machine below is used to control the attenuation of the dac output and the gaining up of the signal again once the trigger is released. figure 43. pap gain state machine the normal operating condition for the pap block is the normal state in figure 43 . however, when the pap block detects an error condition it sets the pap_trig signal to ? 1 ? causing a state transition from normal operation to the attenuate state.
54 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated in the attenutate state the data path gain is scaled from 1.0 down to 0.0 by a programmable step amount set by fields papab_gain_step in register pap_gain_ab ( 8.5.35 ) and papcd_gain_step in register pap_gain_cd ( 8.5.33 ). this value is always positive with the decimal place located between the msb and msb-1. unity is equal to ? 1000000000 ? . each clock cycle (16 samples) the pap_gain is stepped down by papab_gain_step and papcd_gain_step until the gain is 0. after pap_gain is 0, the state machine moves on to the wait state. here a programmable counter counts clock cycles to allow the condition for the pap_trig to be fixed. fields papab_wait in register pap_wait_ab ( 8.5.32 ) and papcd_wait in register pap_wait_cd ( 8.5.34 ) are used to select the number of clock cycles (samples = 16 x papab_wait or 16 x papcd_wait) to wait before moving to the next state. once the wait counter equals zero and pap_trig= ? 0 ? , the state machine moves on to the gain state. if the wait equals 0 but pap_trig still equals ? 1 ? then the state machine stays in the wait state until pap_trig = ? 0 ? . 8.3.19 gain block the gain block also has additional output gain control through fields gainab in register gainab ( 8.5.35 ) and gaincd in register gaincd ( 8.5.40 ). similar to pap_gain value, the output gain is always positive with unity when gainab or gaincd = ? 010000000000 ? . to reduce the power the gain block clock has been gated whenever the pap is disabled and gainab or gaincd is set to unity. 8.3.20 output summation the outsum block allows addition of samples from each duc in the multi-duc. it is also possible to add the output samples from the adjacent multi-duc. field outsum_sel in register outsum ( 8.5.22 ) controls the summation for each multi-duc. the functionality of the block can be represented by the following equation: (7) in order to avoid overflow, rounding operation is performed after the addition to reduce the word size back to 16- bits. exact number of bits rounded depends on the number of channels added. table 39 shows the description of round after the summation. table 39. outsum scaling and rounding # of channels added # of bits rounded 0 0, use bits[15:0] from the result 1 use bits[16:1] from the result and bit[0] used for rounding 2 use bits[17:2] from the result and bits[1:0] used for rounding 3 use bits[18:3] from the result and bit[2:0 used for rounding 4 use bits[19:4] from the result and bit[3:0] used for rounding 8.3.21 output delay the signal following output summation can be programmably delayed by 0-15 dacclk cycles through field output_delay in register outsum ( 8.5.20 ). the block takes 16 sample words (vec16) from both the a and b paths and shifts the them to 32 sample long delay line. 8.3.22 polarity inversion the signal following the output delay can be inverted by a 2 ? s complement conversion allowing the + and - dac outputs to be swapped by asserting field dac_complement in register multiduc_cfg1 ( 8.5.13 ). 8.3.23 temperature sensor the dac38rfxx incorporates a temperature sensor block which monitors the die temperature by measuring the voltage across 2 transistors. the voltage is converted to an 8-bit digital word using a successive approximation (sar) analog to digital conversion process. the result is scaled, limited and formatted as a twos complement value representing the temperature in degrees celsius. output ab cd ab cd outsum same same adj adj
55 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated the sampling is controlled by the serial interface signals sden and sclk. if the temperature sensor is enabled by writing a 0 to field tsense_sleep in register sleep_config ( 8.5.70 ), a conversion takes place each time the serial port is written or read. the data is only read and sent out by the digital block when the temperature sensor is read in field tempdata in register temp_pllvolt ( 8.5.7 ). the conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth sclk. the data is then clocked out of the chip on the rising edge of the ninth sclk. no other clocks to the chip are necessary for the temperature sensor operation. as a result the temperature sensor is enabled even when the device is in sleep mode. in order for the process described above to operate properly, the serial port read from register temp_pllvolt must be done with an sclk period of at least 1 s. if this is not satisfied the temperature sensor accuracy is greatly reduced. 8.3.24 alarm monitoring the dac38rfxx includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction scenario. all the alarm events can be accessed either through the sip registers and/or through the alarm output. once an alarm is set, the corresponding alarm bit must be reset through the serial interface to allow further testing. the set of alarms includes the following conditions: ? jesd alarms ? fields alm_lanex_err in registers jesd_alm_lx (x = 0-7, 8.5.59 to 8.5.66 ): ? multiframe alignment_error. occurs when multiframe alignment fails ? frame alignment error. occurs when multiframe alignment fails ? link configuration error. occurs when there is wrong link configuration ? elastic buffer overflow. occurs when bad rbd value is used ? elastic buffer match error. occurs when the first non-/k/ doesn ? t match the programmed data ? code synchronization error ? 8b/10b not-in-table decode error ? 8b/10b disparity error ? field alm_from_shorttest in register alm_sysref_pap ( 8.5.67 ): occurs when the short pattern test fails. ? serdes alarms ? field alm_sd_lotdet in register alm_sd_det 8.5.5 ): occurs when there are loss of signal detect from serdes lanes. ? fields alm_fifox_flags in registers jesd_alm_lx (x = 0-7, 8.5.59 to 8.5.66 ): ? fifo write error. occurs if write request and fifo is full. ? fifo write full: occurs if fifo is full. ? fifo read error. occurs if read request and fifo is empty. ? fifo read empty: occurs if fifo is empty. ? field alm_sd0_pll in register alm_sysref_det ( 8.5.6 ): occurs if the pll in the serdes block 0 goes out of lock. ? field alm_sd1_pll in register alm_sysref_det ( 8.5.6 ): occurs if the pll in the serdes block 1 goes out of lock. ? sysref alarm ? field alm_sysref_err in register alm_sysref_pap ( 8.5.67 ): occurs when the sysref is received at an unexpected time. if too many of these occur it will cause the jesd to go into synchronization mode again. ? dac pll alarm ? field pll_lock in register alm_sysref_det ( 8.5.6 ). this register field is asserted when the pll is locked. when used as an alarm output, this is inverted so a high signal indicated that the pll is unlocked. ? pap alarm ? field alm_pap in register alm_sysref_pap ( 8.5.67 ): occurs when the average power is above the threshold. while any alarm_pap is asserted the attenuation for the appropriate data path is applied.
56 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.25 differential clock inputs figure 44 shows the preferred configuration for driving the dacclk+/- and sysref+/- with a differential ecl/pecl source. figure 44. preferred clock input configuration with a differential ecl/pecl clock source lvpcl driver 240 w 240 w 100 w 0.01 f m 0.01 f m c ac copyright ? 2016, texas instruments incorporated
57 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3.26 cmos digital inputs figure 45 shows a schematic of the equivalent cmos digital inputs of the dac38rfxx. sdio, sclk, tclk, sleep, testmode and txenable have internal pull-down resistors while sden, reset, tms, tdi and trst have internal pull-up resistors. see the specifications table for logic thresholds. the pull-up and pull-down circuitry is approximately equivalent to 10 k . figure 45. cmos digital equivalent input 8.3.27 dac fullscale output current the dac38rfxx uses a bandgap reference and control amplifier for biasing the full-scale output current. the dac full scale output current is set by a combination of the fixed current through the external resistor rbias (connected to pin biasj) and current from course trim current sources: (8) the bias current ibias through resistor r bias is defined by the on-chip bandgap reference voltage v bg (nominally 0.9 v) and control amplifier. for normal operation, it is recommended that r bias is set to 3.6 k for a fixed current through r bias of 250 a. this current is scaled 128x internally, giving: (9) the course trim current sources are configured through spi register field dacfs in register dacfs ( 9.5.69 ),as follows: (10) from the discussion above, the dac full scale output current can be configured from 40 ma (dacfs[3:0] = 1111) down to 10 ma (dacfs[3:0] = 0000). an external decoupling capacitor c ext of 0.1 f should be connected externally to terminal extio for compensation. r bias of 3.6 k is recommended for setting the full-scale output current. 8.3.28 current steering dac architecture the dacs in the dac38rfxx consist of a segmented array of nmos current sources, capable of sinking a full- scale output current up to 40 ma (see figure 46 ). differential current switches direct the current to either one of the complimentary output nodes vout1/2+ or vout1/2-. these complementary output nodes are internal to the device because of the integrated balun.complimentary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and pcb noise), dc offsets, even order distortion components, and increasing signal output power by a factor of four. coarsetrim i = 2ma dacfs - 11 bg rbias bias v v i ma r k 0.9 128 128 32 3.6 u u fs rbias coarsetrim iout i i sdio sclk tclk sleep txenable testmode internal digital in vddio18 gnd sdenb resetb tms tdi trstb internal digital in vddio18 gnd 400 400 10 k 10 k copyright ? 2016, texas instruments incorporated
58 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 46. current steering dac architecture referring to figure 46 , the total output current ioutfs is fixed, and is switched to either the + or ? output by switches s(n): (11) since the output stage is a current sinking architecture, we will denote current into the dac as + current, and the current flows iout+ and iout- into terminals vout1/2+ and vout1/2- respectively. iout+ and iout- can be expressed as: (12) (13) where code is the decimal representation of the 14-bit dac core data input word. note the signal path up to the dac is 16-bits and the 2 lsbs are truncated for the dac core data input word. 8.3.29 dac transfer function the dac38rfxx has a wide bandwidth integrated balun (nominally 700 mhz to 3.8 ghz passband) to convert the dac core differential signal to a single ended signal. the single ended output is expected to drive a 50- load (see figure 47 ). with full-scale current of 40 ma, the theoretical output power delivered to a 50 ohms load is 4 dbm. however the actual power delivered will be less than the theoretical value and figure 19 shows the output power across frequency. fs iout code iout- 16383 16384 u fs iout code iout+ 16384 u fs iout iout + iout- vdee18n (-1.8v) vout1/2+ vout1/2- 100 : zext+ zext- vddout18 iout+ iout-
59 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 47. driving a 50- load 8.4 device functional modes 8.4.1 clocking modes the dac38rfxx has both a single ended clock input dacclkse and a differential clock input dacclk+/- to clock the device. the clock input is selected by field sel_extclk_diffse in register clk_pll_cfg ( 8.5.79 ). the dac38rfxx can be clocked directly with a high frequency input clock at the dac sample rate (pll bypass mode), or an optional on-chip low-jitter phase-locked loop (pll) can be used to generate the high frequency dac sample clock internally from a lower frequency reference clock input (pll mode). 8.4.2 pll bypass mode programming in pll bypass mode a high quality clock is sourced to the dacclk inputs. this clock is used to directly clock the dac38rfxx dac cores. this mode gives the device best performance and is recommended for extremely demanding applications. the bypass mode is selected by setting the following: 1. set field pll_ena in register clk_pll_cfg ( 8.5.79 ) to ? 0 ? to bypass the pll circuitry. 2. set field pll_sleep in register sleep_config ( 8.5.70 ) to ? 1 ? to put the pll and vco into sleep mode. 8.4.3 internal pll/vco the dac38rfxx has an internal clock generation circuit consisting of a pll and two identical vcos connected in parallel, as shown in figure 48 . figure 48. internal pll/vco block diagram n pfd and charge pump output buffer 4 m pll_m(7-0) pll_n(4-0) vco vco dac clk 50 : r load vout1/2
60 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) the two parallel vcos are tuned to a target center frequency of 5.9 ghz (low vco) in dac38rf87 and dac38rf97. they are tuned to a target center frequency of 8.85 ghz (high vco) in dac38rf86 and dac38rf96. the field pll_vcosel in register pll_config2 ( 8.5.81 )must always be set to 0 in dac38rf87/97 and always set to '1' in dac38rf86/96/88/81. also gsmpll_ena in register pll_config2 must always be set to '1' in all devices to ensure the two identical vcos are connected in parallel. the 7 bit vco tuning code in field pll_vco in register pll_config2 is used to tune the vco frequency in the range of 5.24 ghz to 6.72 ghz for the low vco and 7.96 ghz to 9.0 ghz for the high vco. for the low vco the center vco frequency is achieved with pll_vco = 63 decimal and for the high vco the target vco center frequency is also achieved with pll_vco = 63 decimal . the supply current, and therefore; the analog signal amplitude in the vco is controlled using the field pll_vco_rdac in register pll_config1 ( 8.5.80 ). this control signal should be set 15 decimal initially for 18 ma supply current in the vco and ~1.4 v pp single ended oscillation amplitude. the pll has no prescaler, so the dac sample rate is the vco frequency. in the pll feedback path a fixed 4 frequency divider block receives the vco output clock and divides its frequency by 4. the maximum operating frequency of the phase-frequency detector (pfd) is approximately 550 mhz. the m (feedback) clock divider takes the output clock signal from the fixed 4 block and divides it by a programmable ratio set by the 8-bit field in field pll_m_m1 in register pll_config1 ( 8.5.80 ). the programmable division ratio range is 1 to 256, and is the value of the 8 bit unsigned binary code + 1. although it is possible to program the m divider to 1, 2 and 3, these values should not be used. as stated previously the pfd and cp have a finite maximum operating frequency, which is the vco frequency divided by the fixed divider ratio multiplied by the minimum allowable m divider ratio. (14) the n (reference) divider determines the ratio between the input reference clock frequency and the pfd operating frequency, and is set by the 5-bit field pll_n_m1 in register clk_pll_cfg ( 8.5.79 ). the division ratio range is 1 to 32, and is the value of the 5-bit unsigned binary code + 1. the charge pump output current amplitude is set using the 4-bit field pll_cp_adj in in register pll_config2 ( 8.5.81 ). the current amplitude is simply the digital code multiplied by the unit current amplitude of 100 a. in a nominal condition, with the lf vco running at 5.898 ghz, and with the m divider set to 4, the pfd will run at 368.625 mhz, and the change pump current should set to 6 decimal , which gives 600 a charge pump output current for a good phase margin of 69 degrees. if a higher m ratio (for lower pfd frequencies) are required the charge pump output current must be increased to maintain good loop stability and prevent excessive peaking in the phase noise response. the charge pump output current setting pll_cp_adj should be adjusted in relation to the feedback (m) divider ratio pll_m_m1 according to the following table to maintain a constant phase margin of 69 degrees. table 40. m vs kp for maintaining good stability m cp_adj 4 6 6 9 8 12 10 15 similarly for the hf vco running at 8.847 ghz, and with the m divider set to 4, the pfd will run at 552.9375 mhz as shown above. here the change pump current should set to 6 decimal , which gives 600 a charge pump output current for a good phase margin of 69 degrees. 8.4.4 clkout the dac38rfxx has a programmable output clock on clktx+/- balls that is a divided version of the internal dac sample clock, either with or without pll. two frequency dividers, either dacclk/3 or dacclk/4, are available by programming field clk_tx_div4 in register clk_out ( 8.5.71 ). the output swing voltage is programmable from approximately 125 to 1460 mv pp-diff through field clk_tx_swing in register clk_out ( 8.5.71 ). fmax min pfd cp fvco fixed div x mdiv _ / _
61 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated field clk_tx_idle in register clk_out ( 8.5.71 ) enables an idle state, in which the pins are driven to the proper common-mode levels in order to charge the external ac coupling caps but the clock output is disabled. the output clock circuit can be put to sleep by field clk_tx_sleep in register sleep_config ( 8.5.70 ). 8.4.5 serial peripheral interface (spi) the serial port of the dac38rfxx is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. the interface provides read/write access to all registers used to define the operating modes of dac38rfxx. it is compatible with most synchronous transfer formats and can be configured as a 3 or 4 terminal interface by sif4_ena in register io_config ( 8.5.2 ). in both configurations, sclk is the serial interface input clock and sden is serial interface enable. for 3 terminal configuration, sdio is a bidirectional terminal for both data in and data out. for 4 terminal configuration, sdio is bidirectional and sdo is data out only. data is input into the device with the rising edge of sclk. data is output from the device on the falling edge of sclk. the spi registers are reset by writing a 1 to spi_reset in register reset_config ( 8.5.1 ). each read/write operation is framed by signal sden (serial data enable bar) asserted low. the first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. figure 49 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. the data transfer cycle consists of two bytes. figure 49. instruction byte of the serial interface bit 7 (msb) 6 5 4 3 2 1 0 description r/w a6 a5 a4 a3 a2 a1 a0 r/w - identifies the following data transfer cycle as a read or write operation. a high indicates a read operation from dac38rfxx and a low indicates a write operation to dac38rfxx a6:a0 - identifies the address of the register to be accessed during the read or write operation. figure 50 shows the serial interface timing diagram for a dac38rfxx write operation. sclk is the serial interface clock input to dac38rfxx. serial data enable s den is an active low input to dac38rfxx. sdio is serial data input. input data to dac38rfxx is clocked on the rising edges of sclk. figure 50. serial interface write timing diagram figure 51 shows the serial interface timing diagram for a dac38rfxx read operation. sclk is the serial interface clock input to dac38rfxx. serial data enable sden\ is an active low input to dac38rfxx. sdio is serial data input during the instruction cycle. in 3 pin configuration, sdio is data out from the dac38rfxx during the data transfer cycle, while sdo is in a high-impedance state. in 4 pin configuration, both sdio and sdo are data out from the dac38rfxx during the data transfer cycle. at the end of the data transfer, sdio and sdo will output low on the final falling edge of sclk until the rising edge of sden when they will 3-state. rwb a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 instruction cycle data transfer cycle t s (sden\) t s (sdio) t h (sdio) t sclk sden\ sclk sdio sden\ sclk sdio
62 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 51. serial interface read timing diagram n the sif interface there are four types of registers: 8.4.5.1 normal (rw) the normal register type allows data to be written and read from. all 16-bits of the data are registered at the same time. there is no synchronizing with an internal clock thus all register writes are asynchronous with respect to internal clocks. there are three subtypes of normal: 1. autosync: a normal register that causes a sync to be generated after the write is finished. these are used when it is desirable to synchronize the block after writing the register or for a single field that spans across multiple registers. for instance, the nco requires three 16-bit register writes to set the frequency. upon writing the last of these registers an autosync is generated to deliver the entire field to the nco block at once, rather than in pieces after each individual register write. for a field that spans multiple registers, all non-autosync registers for the field must be written first before the actual autosync register. 2. no reset value: these are normal registers, but the reset value cannot be specified. this could be because the register has some read_only bits or some internal logic partially controls the bit values. 3. read_only (r): registers that can only be read. 8.4.5.2 write_to_clear (w0c) these registers are just like normal registers with one exception. they can be written and read, however, when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is written to ? 0 ? . this way interrupts will be captured and stay constant until cleared by the user. 8.5 register maps table 41. register summary address reset acronym register name section general configuration registers (page_set[2:0] = 000) 0x00 0x5803 reset_config chip reset and configuration 8.5.1 0x01 0x1800 io_config io configuration 8.5.2 0x02 0xffff alm_sd_mask lane signal detect alarm mask 8.5.3 0x03 0xffff alm_clk_mask clock alarms mask 8.5.4 0x04 0x0000 alm_sd_det serdes loss of signal detection alarms 8.5.5 0x05 0x0000 alm_sysref_det sysref alignment circuit alarms 8.5.6 0x06 variable temp_pllvolt temperature sensor and pll loop voltage 8.5.7 0x07-0x08 0x0000 reserved reserved 0x09 0x0000 page_set page set 8.5.8 rwb a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 instruction cycle data transfer cycle t d (data) sden\ sclk sdio sden\ sclk sdio sdo d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdo data n data n-1
63 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated register maps (continued) table 41. register summary (continued) address reset acronym register name section 0x0a-0x77 0x0000 reserved reserved 0x78 0x0000 sysref_align_r syserf align to r1 and r3 count 8.5.9 0x79 0x0000 sysref12_cnt sysref phase count 1 and 2 8.5.10 0x7a 0x0000 sysref34_cnt sysref phase count 3 and 4 8.5.11 0x7b-0x7e 0x0000 reserved reserved 0x7f 0x0008 vendor_ver vendor id and chip version 8.5.12 multi-duc configuration registers (page_set[0] = 1 for multi-duc1, page_set[1] = 1 for multi-duc2) 0x0a 0x02b0 multiduc_cfg1 multi-duc configuration (pap, interpolation) 8.5.13 0x0b 0x0000 reserved reserved 0x0c 0x2402 multiduc_cfg2 multi-duc configuration (mixers) 8.5.14 0x0d 0x8300 jesd_fifo jesd fifo control 8.5.15 0x0e 0x00ff alm_mask1 alarm mask 1 8.5.16 0x0f 0x1f83 alm_mask2 alarm mask 2 8.5.17 0x10 0xffff alm_mask3 alarm mask 3 8.5.18 0x11 0xffff alm_mask4 alarm mask 4 8.5.19 0x12 0x0000 jesd_ln_skew jesd lane skew 8.5.20 0x13-0x16 0x0000 reserved reserved 0x17 0x0000 cmix cmix configuration 8.5.21 0x18 0x0000 reserved reserved 0x19 0x0000 outsum output summation and delay 8.5.22 0x1a-0x1b 0x0000 reserved reserved 0x1c 0x0000 phase_ncoab phase offset for ab path nco 8.5.23 0x1d 0x0000 phase_ncocd phase offset for cd path nco 8.5.24 0x1e-0x20 0x0000 freq_ncoab frequency for ab path nco 8.5.25 0x21-0x23 0x0000 freq_ncocd frequency for cd path nco 8.5.26 0x24 0x0010 sysref_clkdiv sysref use for clock divider 8.5.27 0x25 0x7700 serdes_clk serdes clock control 8.5.28 0x26 0x0000 reserved reserved 0x27 0x1144 syncsel1 sync source selection 8.5.29 0x28 0x0000 syncsel2 sync source selection 8.5.30 0x29 0x0000 pap_gain_ab pap path ab gain attenuation step 8.5.31 0x2a 0x0000 pap_wait_ab pap path ab wait time at gain = 0 8.5.32 0x2b 0x0000 pap_gain_cd pap path cd gain attenuation step 8.5.33 0x2c 0x0000 pap_wait_cd pap path cd wait time at gain = 0 8.5.34 0x2d 0x1fff pap_cfg_ab pap path ab configuration 8.5.35 0x2e 0x1fff pap_cfg_cd pap path cd configuration 8.5.36 0x2f 0x0000 spidac_test1 configuration for dac spi constant 8.5.37 0x30 0x0000 spidac_test2 dac spi constant 8.5.38 0x31 0x0000 reserved reserved 0x32 0x0800 gainab gain for path ab 8.5.39 0x33 0x0800 gaincd gain for path cd 8.5.40 0x34-0x40 0x0000 reserved reserved 0x41 0x0000 jesd_err_cnt jesd error counter 8.5.41 0x42-0x45 0x0000 reserved reserved 0x46 0x0044 jesd_id1 jesd id 1 8.5.42 0x47 0x190a jesd_id2 jesd id 2 8.5.43 0x48 0x31c3 jesd_id3 jesd id 3 and subclass 8.5.44 0x49 0x0000 reserved reserved 0x4a 0x0003 jesd_ln_en jesd lane enable 8.5.45 0x4b 0x1300 jesd_rbd_f jesd rbd buffer and frame octets 8.5.46
64 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated register maps (continued) table 41. register summary (continued) address reset acronym register name section 0x4c 0x1303 jesd_k_l jesd k and l parameters 8.5.47 0x4d 0x0100 jesd_m_s jesd m and s parameters 8.5.48 0x4e 0x0f4f jesd_n_hd_scr jesd n, hd and scr parameters 8.5.49 0x4f 0x1cc1 jesd_match jesd character match and other 8.5.50 0x50 0x0000 jesd_link_cfg jesd link configuration data 8.5.51 0x51 0x00ff jesd_sync_req jesd sync request 8.5.52 0x52 0x00ff jesd_err_out jesd error output 8.5.53 0x53 0x0100 jesd_ila_cfg1 jesd configuration value used for ila check 8.5.54 0x54 0x8e60 jesd_ila_cfg2 jesd configuration value used for ila check 8.5.55 0x55-0x5b 0x0000 reserved reserved 0x5c 0x0001 jesd_sysr_mode jesd sysref mode 8.5.56 0x5d-0x5e 0x0000 reserved reserved 0x5f 0x0123 jesd_crossbar1 jesd crossbar configuration 1 8.5.57 0x60 0x4567 jesd_crossbar2 jesd crossbar configuration 2 8.5.58 0x61-0x63 0x0000 reserved reserved 0x64 0x0000 jesd_alm_l0 jesd alarms for lane 0 8.5.59 0x65 0x0000 jesd_ alm_l1 jesd alarms for lane 1 8.5.60 0x66 0x0000 jesd_ alm_l2 jesd alarms for lane 2 8.5.61 0x67 0x0000 jesd_alm_l3 jesd alarms for lane 3 8.5.62 0x68 0x0000 jesd_alm_l4 jesd alarms for lane 4 8.5.63 0x69 0x0000 jesd_alm_l5 jesd alarms for lane 5 8.5.64 0x6a 0x0000 jesd_alm_l6 jesd alarms for lane 6 8.5.65 0x6b 0x0000 jesd_alm_l7 jesd alarms for lane 7 8.5.66 0x6c 0x0000 alm_sysref_pap sysref and pap alarms 8.5.67 0x6d 0x0000 alm_clkdiv1 clock divider alarms 1 8.5.68 0x6e-0x77 0x0000 reserved reserved miscellaneous configuration registers (page_set[1:0] = 00, page_set[2] = 1) 0x0a 0xfc03 clk_config clock configuration 8.5.69 0x0b 0x0022 sleep_config sleep configuration 8.5.70 0x0c 0xa002 clk_out divided output clock configuration 8.5.71 0x0d 0xf000 dacfs dac fullscale current 8.5.72 0x0e-0x0f 0x0000 reserved reserved 0x10 0x0000 lcmgen internal sysref generator 8.5.73 0x11 0x0000 lcmgen_div counter for internal sysref generator 8.5.74 0x12 0x0000 lcmgen_spisysref spi sysref for internal sysref generator 8.5.75 0x13-0x1a 0x0000 reserved reserved 0x1b 0x0000 dtest digital test signals 8.5.76 0x1c-0x22 0x0000 reserved reserved 0x23 0x03f3 sleep_cntl sleep pin control 8.5.77 0x24 0x1000 sysr_capture sysref capture circuit control 8.5.78 0x25-0x30 0x0000 reserved reserved 0x31 0x0200 clk_pll_cfg clock input and pll configuration 8.5.79 0x32 0x0308 pll_config1 pll configuration 1 8.5.80 0x33 0x4018 pll_config2 pll configuration 2 8.5.81 0x34 0x0000 lvds_config lvds output configuration 8.5.82 0x35 0x0018 pll_fdiv fuse farm clock divider 8.5.83 0x36-0x3a 0x0000 reserved reserved 0x3b 0x0002 srds_clk_cfg serdes clock configuration 8.5.84
65 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated register maps (continued) table 41. register summary (continued) address reset acronym register name section 0x3c 0x8228 srds_pll_cfg serdes pll configuration 8.5.85 0x3d 0x0088 srds_cfg1 serdes configuration 1 8.5.86 0x3e 0x0909 srds_cfg2 serdes configuration 2 8.5.87 0x3f 0x0000 srds_pol serdes polarity control 8.5.88 0x40-0x75 0x0000 reserved reserved 0x76 0x0000 syncbout jesd204b syncb output 8.5.89
66 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.1 chip reset and configuration register (address = 0x00) [reset = 0x5803] figure 52. chip reset and configuration register (reset_config) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw legend: r/w = read/write; r = read only; -n = value after reset table 42. reset_config field descriptions bit field type reset description 15 spi_reset rw 0 this will reset all the spi registers once programmed. 14 alm_out_pol rw 1 changes the polarity of the alarm output. 0= active low 1= active high 13 alm_out_ena rw 0 turn on the alarm pin 12 sysclk_ena rw 1 turns on the dividers for the sysclk to the fusefarm 11 autoload_trig rw 1 causes a fuse autoload to be executed. 10:7 reserved rw 0000 reserved 6 one_dac_only rw 0 when set high only the slice0 is available. 5 one_link_only rw 0 this needs to be set high when a single link setup is being programmed to get the correct txenable signal generation 4:2 reserved rw 000 reserved 1 init_slice1 rw 1 puts the multi-dac2 jesd into initialization state 0 init_slice0 rw 1 puts the multi-dac1 jesd into initialization state
67 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.2 io configuration register (address = 0x01) [reset = 0x1800] figure 53. io configuration register (io_config) 15 14 13 12 11 10 9 8 0 0 0 1 1 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 43. io_config field descriptions bit field type reset description 15:14 gpo0_sel rw 00 selects the jesd sync_n signal coming out the gpo0 pin. both bits can be asserted which does an oring of the sync_n signals from each multi-duc. bit 0 = 1 then multi-duc1 sync_n used bit 1 = 1 then multi-duc2 sync_n is used 13:12 sync0b_sel rw 01 selects the jesd sync_n signal coming out the sync0b pin. both bits can be asserted which does an oring of the sync_n signals from each multi-duc. bit 0 = 1 then multi-duc1 sync_n used bit 1 = 1 then multi-duc2 sync_n is used 11:10 sync1b_sel rw 10 selects the jesd sync_n signal coming out the sync1b pin. both bits can be asserted which does an oring of the sync_n signals from each multi-duc. bit 0 = 1 then multi-duc1 sync_n used bit 1 = 1 then multi-duc2 sync_n is used 9:8 gpo1_sel rw 00 selects the jesd sync_n signal coming out the gpo1 pin. both bits can be asserted which does an oring of the sync_n signals from each multi-duc. bit 0 = 1 then multi-duc1 sync_n used bit 1 = 1 then multi-duc2 sync_n is used 7 spi4_ena rw 0 when set to a '1' the chip is in 4 pin spi interface mode. 6 reserved rw 0 reserved 5:0 atest rw 000000 select the analog test points: 000000: atest is off (atest must be off during normal operation) 000001, 010001, 000110: vssclk 000010: vddpll1 000101: vddclk 000111, 001010, 010000: vddapll18 001011: vddavco18 001101: vdds18 001110: vdde1 001111, 111010, 111011, 111100: dgnd 010011: vddtx1 101001, 110001: agnd 101111, 111101, 111110, 11111: vdddig1 110000: vdda18
68 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.3 lane single detect alarm mask register (address = 0x02) [reset = 0xffff] figure 54. lane single detect alarm mask register (alm_sd_mask) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 44. alm_sd_mask field descriptions bit field type reset description 15:0 alm_sd_mask r/w 0xffff used to mask alarms bit 15 - bit 8 : reserved bit7 : lane 7 loss of signal detect bit6 : lane 6 loss of signal detect bit5 : lane 5 loss of signal detect bit4 : lane 4 loss of signal detect bit3 : lane 3 loss of signal detect bit2 : lane 2 loss of signal detect bit1 : lane1 loss of signal detect bit0 : lane 0 loss of signal detect 8.5.4 clock alarms mask register (address = 0x03) [reset = 0xffff figure 55. clock alarms mask register (alm_clk_mask) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 45. alm_clk_mask field descriptions bit field type reset description 15:0 alm_clk_mask r/w 0xffff used to mask alarms bit 15 - bit 8 : reserved bit 7 : alarm_sysrefphase4 bit 6 : alarm_sysrefphase3 bit 5 : alarm_sysrefphase2 bit 4 : alarm_sysrefphase1 bit 3 : alarm_align_to_r3 bit 2 : alarm_align_to_r1 bit 1 : alarm_sd0_pll bit 0 : alarm_sd1_pll
69 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.5 serdes loss of signal detection alarms register (address = 0x04) [reset = 0x0000] figure 56. serdes loss of signal detection alarms register (alm_sd_det) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset table 46. alm_sd_det field descriptions bit field type reset description 15:8 reserved w0c 0x00 reserved 7:0 alm_sd_losdet w0c 0x00 loss of signal detect outputs from the serdes lanes: bit 7 = lane7 loss of signal bit 6 = lane6 loss of signal bit 5 = lane5 loss of signal bit 4 = lane4 loss of signal bit 3 = lane3 loss of signal bit 2 = lane2 loss of signal bit 1 = lane1 loss of signal bit 0 = lane0 loss of signal
70 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.6 sysref alignment circuit alarms register (address = 0x05) [reset = 0x0000] figure 57. sysref alignment circuit alarms register (alm_sysref_det) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset table 47. alm_sysref_det field descriptions bit field type reset description 15:9 reserved w0c 0000000 reserved 8 alm_sysrphase4 w0c 0 if high the sysrefphase4 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync. 7 alm_sysrphase3 w0c 0 if high the sysrefphase3 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync. 6 alm_sysrphase2 w0c 0 if high the sysrefphase2 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync. 5 alm_sysrphase1 w0c 0 if high the sysrefphase1 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync. 4 alm_align_to_r3 w0c 0 if high the align_to_r3 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync. ti internal use only. 3 alm_align_to_r1 w0c 0 if high the align_to_r1 state has been observed in the sysrefalign logic at least once since the last sysrefalign sync. ti internal use only. 2 alm_sd0_pll w0c 0 driven high if the pll in the serdes 0 block goes out of lock. a false alarm is generated at startup when the pll is locking. user will have to reset this bit after start to monitor accurately. 1 alm_sd1_pll w0c 0 driven high if the pll in the serdes 1 block goes out of lock. a false alarm is generated at startup when the pll is locking. user will have to reset this bit after start to monitor accurately. 0 pll_lock w0c 0 asserted when pll is unlocked.
71 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.7 temperature sensor and pll loop voltage register (address = 0x06) [reset = variable] figure 58. temperature sensor and pll loop voltage register (temp_pllvolt) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 48. temp_pllvolt field descriptions bit field type reset description 15:8 tempdata r 0x00 8 bits of data from the tempurature sensor 7:5 pll_lfvolt r 0b000 pll loop filter voltage 4:2 reserved r 0b000 reserved 1 titest_voh r 1 a fixed '1' that can be used to test the voh condition on sdo/sdio. 0 titest_vol r 0 a fixed '0' that can be used to test the vol condition on sdo/sdio. 8.5.8 page set register (address = 0x09) [reset = 0x0000] figure 59. page set register (page_set) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 49. page_set field descriptions bit field type reset description 15:0 page_set r/w 0x0000 each bit selects a page that is active. multiple pages can be selected at the same time. no bits asserted means that master is the only page selected. bit 0 = page0 : multi-duc1 bit 1 = page1 : multi-duc2 bit 2 = page2 : dig_misc bit 3-15: reserved
72 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.9 sysref align to r1 and r3 count register (address = 0x78) [reset = 0x0000] figure 60. sysref align to r1 and r3 count register (sysref_align_r) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r r r r r r r r 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 50. sysref_align_r field descriptions bit field type reset description 15:8 align_to_r1_cnt r 0x00 part of the sysref align block 7:0 align_to_r3_cnt r 0x00 part of the sysref align block 8.5.10 sysref phase count 1 and 2 register (address = 0x79) [reset = 0x0000] figure 61. sysref phase count 1 and 2 register (sysref12_cnt) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r r r r r r r r 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 1 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 51. sysref12_cnt field descriptions bit field type reset description 15:8 phase2_cnt r 0x00 part of the sysref align block 7:0 phase1_cnt r 0x00 part of the sysref align block
73 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.11 sysref phase count 3 and 4 register (address = 0x7a) [reset = 0x0000] figure 62. sysref phase count 3 and 4 register (sysref34_cnt) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r r r r r r r r 7 6 5 4 3 2 1 0 0 1 1 1 1 0 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 52. sysref34_cnt field descriptions bit field type reset description 15:8 phase4_cnt r 0x00 part of the sysref align block 7:0 phase3_cnt r 0x00 part of the sysref align block 8.5.12 vendor id and chip version register (address = 0x7f) [reset = 0x0008]] figure 63. vendor id and chip version register (vendor_ver) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r r r r r r r r 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 53. vendor_ver field descriptions bit field type reset description 15 autoload_done r 0 asserted when the fusefarm autoload sequence is done 14:10 efc_err r 00000 the error output from the fuse farm. 9:5 reserved r 00000 reserved 4:3 vendorid r 01 ti identification 2:0 version r 001 bits to determine what version of build for the chip.
74 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.13 multi-duc configuration (pap, interpolation) register (address = 0x0a) [reset = 0x02b0] figure 64. multi-duc configuration (pap, interolation) register (multiduc_cfg1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 54. multiduc_cfg1 field descriptions bit field type reset description 15 dual_iq r/w 0 when asserted the slice uses both iq paths 14 isfir_ena r/w 0 turns on the inverse sync filter for the ab and cd paths when programmed to 1. 13 not used r/w 0 not used 12:8 interp r/w 00010 determines the interpolation amount. 00000: 1x 00001: 2x 00010: 4x 00011: 6x 00100: 8x 00101: 10x 00110: 12x 01000: 16x 01001: 18x 01010: 20x 01100: 24x 7 alm_zeros_txen r/w 1 when asserted any alarm that isn ? t masked will mid-level the dac output by setting the txenable_from_dig to ? 0 ? 6 dac_complement r/w 0 when asserted the dac output will be 2's complemented. this helps with hookup at the board level. 5 alm_zeros_jesd r/w 1 when asserted any alarm that isn ? t masked will zero the data coming out of the jesd block. 4 alm_out_ena r/w 1 when asserted the output from the selected slice will be passed on to the master alarm control if it is also turned on then the alarm will be sent to the pad_alarm pin. 3 papa_ena r/w 0 turns on the power amp protection logic for path a. 2 papb_ena r/w 0 turns on the power amp protection logic for path b. 1 papc_ena r/w 0 turns on the power amp protection logic for path c. 0 papd_ena r/w 0 turns on the power amp protection logic for path d.
75 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.14 multi-duc configuration (mixers) register (address = 0x0c) [reset = 0x2402] figure 65. multi-duc configuration (mixers) register (multiduc_cfg2) 15 14 13 12 11 10 9 8 0 0 0 0 0 1 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 55. multiduc_cfg2 field descriptions bit field type reset description 15:14 dac_bitwidth r/w 0b00 determines the bit width of the data going to the dac 00: 14 bits 01: 14 bits 10: 12 bits 11: 11 bits 13 zero_invld_data r/w 1 when asserted; the data from the jesd block is zeroed in the mapper to prevent goofy output from the dac. for test purposes this bit should be desasserted 12 shorttest_ena r/w 0 turns on the jesd short pattern test (5.1.6.2) 11 bist_ena r/w 0 turns on the bist blocks in the slice. 10 bist_zero r/w 1 zeros out the bists captures. 9 mixerab_ena r/w 0 turns on the mixer for the a and b streams 8 mixercd_ena r/w 0 turns on the mixer for the c and d streams 7 mixerab_gain r/w 0 adds 6db of gain when asserted 6 mixercd_gain r/w 0 adds 6db of gain when asserted 5 ncoab_ena r/w 0 when high the full nco block is turned on. 4 ncocd_ena r/w 0 when high the full nco block is turned on. 3:2 reserved r/w 00 reserved 1 twos r/w 1 when asserted the chip is expecting 2's complement data is arriving through the jesd; otherwise offset binary is expected 0 reserved r/w 0 reserved
76 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.15 jesd fifo control register (address = 0x0d) [reset = 0x1300] figure 66. jesd fifo control register (jesd_fifo) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 56. jesd_fifo field descriptions bit field type reset description 15 fifo_zeros_data r/w 1 when asserted fifo errors zero the data out of the jesd block. for test purposes this could be turned off to allow test patterns in the fifo. 14:13 not used r/w 000 not used 12 srds_fifo_alm_clr r/w 0 set to 1 to clear fifo errors. must be set to 0 for proper fifo operation 11 not used r/w 0 not used 10:8 fifo_offset r/w 0000 used to set the difference between read and write pointers in the jesd fifo. 7:1 reserved r/w 0 reserved 0 spi_txenable r/w 0 when asserted the internal value of txenable = '1' 8.5.16 alarm mask 1 register (address = 0x0e) [reset = 0x00ff] figure 67. alarm mask 1 register (alm_mask1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 57. alm_mask1 field descriptions bit field type reset description 15:0 alm_mask1 r/w 0x00ff each bit is used to mask an alarm. assertion masks the alarm: bit 15 = mask lane7 lane errors bit 14 = mask lane6 lane errors bit 13 = mask lane5 lane errors bit 12 = mask lane4 lane errors bit 11 = mask lane3 lane errors bit 10 = mask lane2 lane errors bit 9 = mask lane1 lane errors bit 8 = mask lane0 lane errors bit 7 = mask lane7 fifo flags bit 6 = mask lane6 fifo flags bit 5 = mask lane5 fifo flags bit 4 = mask lane4 fifo flags bit 3 = mask lane3 fifo flags bit 2 = mask lane2 fifo flags bit 1 = mask lane1 fifo flags bit 0 = mask lane0 fifo flags
77 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.17 alarm mask 2 register (address = 0x0f) [reset = 0xffff] figure 68. alarm mask 2 register (alm_mask2) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 58. alm_mask2 field descriptions bit field type reset description 15:0 alms_mask2 r/w 0xffff each bit is used to mask an alarm. assertion masks the alarm: bit 15 = not used bit 14 = not used bit 13 = not used bit 12 = mask sysref errors on link0 bit 11 = mask alarm from jesd shorttest bit 10 = mask alarm from papd bit 9 = mask alarm from papc bit 8 = mask alarm from papb bit 7 = mask alarm from papa bit 6 = not used bit 5 = not used bit 4 = not used bit 3 = not used bit 2 = not used bit 1 = mask alarm_clkdiv192_eq_zero bit 0 = mask alarm_clkdiv192_eq_mult1
78 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.18 alarm mask 3 register (address = 0x10) [reset = 0xffff] figure 69. alarm mask 3 register (alm_mask3) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 59. alm_mask3 field descriptions bit field type reset description 15:0 alms_mask3 r/w 0xffff each bit is used to mask an alarm. assertion masks the alarm: bit 15 = mask alarm_clkdiv8_eq_zero bit 14 = mask alarm_clkdiv12_eq_zero bit 13 = mask alarm_clkdiv16_eq_zero bit 12 = mask alarm_clkdiv18_eq_zero bit 11 = mask alarm_clkdiv20_eq_zero bit 10 = mask alarm_clkdiv32_eq_zero bit 9 = mask alarm_clkdiv36_eq_zero bit 8 = mask alarm_clkdiv40_eq_zero bit 7 = mask alarm_clkdiv48_eq_zero bit 6 = mask alarm_clkdiv64_eq_zero bit 5 = mask alarm_clkdiv72_eq_zero bit 4 = mask alarm_clkdiv80_eq_zero bit 3 = mask alarm_clkdiv96_eq_zero bit 2 = maskalarm_ clkdiv128_eq_zero bit 1 = mask alarm_clkdiv144_eq_zero bit 0 = mask alarm_clkdiv160_eq_zero
79 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.19 alarm mask 4 register (address = 0x11) [reset = 0xffff] figure 70. alarm mask 4 register (alm_mask4) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 60. alm_mask4 field descriptions bit field type reset description 15:0 alms_mask4 r/w 0xffff each bit is used to mask an alarm. assertion masks the alarm: bit 15 = mask alarm_clkdiv8_eq_mult1 bit 14 = mask alarm_clkdiv12_eq_mult1 bit 13 = mask alarm_clkdiv16_eq_mult1 bit 12 = mask alarm_clkdiv18_eq_mult1 bit 11 = mask alarm_clkdiv20_eq_mult1 bit 10 = mask alarm_clkdiv32_eq_mult1 bit 9 = mask alarm_clkdiv36_eq_mult1 bit 8 = mask alarm_clkdiv40_eq_mult1 bit 7 = mask alarm_clkdiv48_eq_mult1 bit 6 = mask alarm_clkdiv64_eq_mult1 bit 5 = mask alarm_clkdiv72_eq_mult1 bit 4 = mask alarm_clkdiv80_eq_mult1 bit 3 = mask alarm_clkdiv96_eq_mult1 bit 2 = maskalarm_ clkdiv128_eq_mult1 bit 1 = mask alarm_clkdiv144_eq_mult1 bit 0 = mask alarm_clkdiv160_eq_mult1
80 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.20 jesd lane skew register (address = 0x12) [reset = 0x0000] figure 71. jesd lane skew register (jesd_ln_skew) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 61. jesd_ln_skew field descriptions bit field type reset description 15:5 not used r 0x0000 not used 4:0 memin_lane_skew r 0b00000 measure of the lane skew for each link only. bits are read_only 8.5.21 cmix configuration register (address = 0x17) [reset = 0x0000] figure 72. cmix configuration register (cmix) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 62. cmix field descriptions bit field type reset description 15:12 cmix_ab r/w 0x0 these bits turn on the different coarse mixing options. combining the different options together can result in every possible n x fs/8 [n=0- > 7]. below is the valid programming table: cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4) 0000 : no mixing 0001 : -fs/4 0010 : fs/2 0100 : fs/4 1000 : fs/8 1100 : 3fs/8 1010 : 5fs/8 1110 : 7fs/8 11:4 reserved r/w 00000000 0 reserved 3:0 cmix_cd r/w 0x0 these bits turn on the different coarse mixing options. combining the different options together can result in every possible n x fs/8 [n=0- > 7]. below is the valid programming table: cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4) 0000 : no mixing 0001 : -fs/4 0010 : fs/2 0100 : fs/4 1000 : fs/8 1100 : 3fs/8 1010 : 5fs/8 1110 : 7fs/8
81 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.22 output summation and delay register (address = 0x19) [reset = 0x0000] figure 73. output summation and delay register (outsum) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 63. outsum field descriptions bit field type reset description 15:12 output_delay r/w 0x0 delays the output to the dac 0 to 15 clock cycles 11:4 reserved r/w 0x00 reserved 3:0 outsum_sel r/w 0x0 selects the output summing functions. each bit selects another sample to sum. multiple bits can be selected. bit 0 = add the isfirab bit 1 = add the isfircb bit 2 = add adjacent slice ab sample bit 3 = add adjacent slice cd sample 8.5.23 nco phase path ab register (address = 0x1c) [reset = 0x0000] figure 74. nco phase path ab register (phase_ncoab) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 1 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 64. phase_ncoab field descriptions bit field type reset description 15:0 phase_nco1 auto sync 0x0000 the phase offset for the full nco1 in the ab datapath. 8.5.24 nco phase path cd register (address = 0x1d) [reset = 0x0000] figure 75. nco phase path cd register (phase_ncocd) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 65. phase_ncocd field descriptions bit field type reset description 15:0 phase_nco12 auto sync 0x0000 the phase offset for the full nco2 in the cd datapath.
82 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.25 nco frequency path ab register (address = 0x1e-0x20) [reset = 0x0000 0000 0000] figure 76. nco frequency path ab register (freq_ncoab) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 66. freq_ncoab field descriptions bit field type reset description 47:0 freq_ncoab r/w 0x0000 0000 0000 nco frequency word for ab data path. 8.5.26 nco frequency path cd register (address = 0x21-0x23) [reset = 0x0000 0000 0000] figure 77. nco frequency path cd register (freq_ncocd) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 67. freq_ncocd field descriptions bit field type reset description 47:0 freq_ncocd r/w 0x0000 0000 0000 nco frequency word for cd data path.
83 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.27 sysref use for clock divider register (address = 0x24) [reset = 0x0010] figure 78. sysref use for clock divder register (sysref_clkdiv) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 68. sysref_clkdiv field descriptions bit field type reset description 15 reserved r/w 0 reserved 14:12 cdrvser_sysref_dly r/w 000 programmable delay the sysref by n dacclk cycles to the cdrv_ser clock dividers. by offsetting the clock to the different multi-duc blocks, clock mixing could potentially be reduced. 11:7 not used r/w 00000 not used 6:4 sysref_mode r/w 001 determines how sysref is used to sync the clock dividers in the cdrv_ser block. 000 = don ? t use sysref pulse 001 = use all sysref pulses 010 = use only the next sysref pulse 011 = skip one sysref pulse then use only the next one 100 = skip one sysref pulse then use all pulses. 3:2 sysref_dly r/w 00 delays the sysref into the cdrv_ser capture ff through 1 of 4 choices. this allows for extra delay in case the timing of the clock or sysref path isn ? t as good as we think. 1:0 reserved r/w 00 reserved
84 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.28 serdes clock control register (address = 0x25) [reset = 0x7700] figure 79. serdes clock control register (serdes_clk) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 69. serdes_clk field descriptions bit field type reset description 15:12 clkjesd_div r/w 0x7 this controls the selection of the clk_jesd output 0000 = div4 0001 = div8 0010 = div12 0011 = div16 0100 = div18 0101 = div20 0110 = div24 0111 = div32 1001 = div36 1010 = div48 1011 = div64 1100 = div5.333 1101 = div10.666 1110 = div21p333 11:8 clkjesd_out_div r/w 0x7 this controls the selection of the clk_jesd_out output 0000 = div8 0001 = div16 0010 = div32 0011 = div48 0100 = div64 0101 = div80 0110 = div96 0111 = div128 1000 = div144 1001 = div160 1010 = div192 7:0 reserved r/w 0x0 reserved
85 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.29 sync source control 1 register (address = 0x27) [reset = 0x1144] figure 80. sync source control 1 register (syncsel1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 70. syncsel1 field descriptions bit field type reset description 15:12 syncsel_mixerab r/w 0x1 controls the syncing of the double buffered spi registers for the mixerab block. these bits are enables so a ? 1 ? in the bit place allows the sync to pass to the block. bit 0 = auto-sync from spi register write bit 1 = sysref bit 2 = sync_out from jesd bit 3 = mem_spi_sync 11:8 syncsel_mixercd r/w 0x1 controls the syncing of the double buffered spi registers for the mixercd block. these bits are enables so a ? 1 ? in the bit place allows the sync to pass to the block. bit 0 = auto-sync from spi register write bit 1 = sysref bit 2 = sync_out from jesd bit 3 = mem_spi_sync 7:4 syncsel_ncoab r/w 0x4 controls the syncing of ncoab accumulators. these bits are enables so a ? 1 ? in the bit place allows the sync to pass to the block. bit 0 = ? 0 ? bit 1 = sysref bit 2 = sync_out from jesd bit 3 = mem_spi_sync 3:0 syncsel_ncocd r/w 0x4 controls the syncing of ncocd accumulators. these bits are enables so a ? 1 ? in the bit place allows the sync to pass to the block. bit 0 = ? 0 ? bit 1 = sysref bit 2 = sync_out from jesd bit 3 = mem_spi_sync
86 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.30 sync source control 2 register (address = 0x28) [reset = 0x0000] figure 81. sync source control 2 register (syncsel2) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 71. syncsel2 field descriptions bit field type reset description 15:12 reserved r/w 0x0 reserved 11:8 syncsel_papab r/w 0x0 select the sync for the pap a and b. bit 0 = ? 0 ? bit 1 = sysref bit 2 = sync_out from jesd bit 3 = mem_spi_sync 7:4 syncsel_papcd r/w 0x0 select the sync for the pap c and d. bit 0 = ? 0 ? bit 1 = sysref bit 2 = sync_out from jesd bit 3 = mem_spi_sync 3:2 reserved r/w 0b00 reserved 1 spi_sync r/w 0 this is used to generate the spi_sync signal 0 reserved r/w 0 reserved 8.5.31 pap path ab gain attenuation step register (address = 0x29) [reset = 0x0000] figure 82. pap path ab gain attenuation step register (pap_gain_ab) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 72. pap_gain_ab field descriptions bit field type reset description 15:10 not used rw 000000 not used 9:0 papab_gain_step 0x000 gain attenuation step
87 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.32 pap path ab wait time register (address = 0x2a) [reset = 0x0000] figure 83. pap path ab wait time register (pap_wait_ab) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 1 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 73. pap_wait_ab field descriptions bit field type reset description 15:10 reserved 000000 r/w reserved 9:0 papab_wait 0x000 r/w number of clock cycles to wait after gain = 0 8.5.33 pap path cd gain attenuation step register (address = 0x2b) [reset = 0x0000] figure 84. pap path cd gain attenuation step register (pap_gain_cd) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 74. pap_gain_cd field descriptions bit field type reset description 15:10 not used r/w 000000 not used 9:0 papcd_gain_step r/w 0x000 gain attenuation step 8.5.34 pap path cd wait time register (address = 0x2c) [reset = 0x0000] figure 85. pap path cd wait time register (pap_wait_cd) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 75. pap_wait_cd field descriptions bit field type reset description 15:10 reserved r/w 000000 reserved 9:0 papcd_wait r/w 0x000 number of clock cycles to wait after gain = 0
88 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.35 pap path ab configuration register (address = 0x2d) [reset = 0x0fff] figure 86. pap path ab configuration register (pap_cfg_ab) 15 14 13 12 11 10 9 8 0 0 reserved 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 76. pap_cfg_ab field descriptions bit field type reset description 15:14 papab_sel_dly r/w 00 controls the length of the delayline in the pap ab logic. 00 : n =32 01 : n = 64 10 : n = 128 11 : not valid 13 reserved r/w 0 reserved 12:0 papab_thresh r/w 0xfff the threshold for the pap ab trigger. 8.5.36 pap path cd configuration register (address = 0x2e) [reset = 0x0fff] figure 87. pap path cd configuration register (pap_cfg_cd) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 77. pap_cfg_cd field descriptions bit field type reset description 15:14 papcd_sel_dly r/w 00 controls the length of the delay line in the pap cd logic. 00 : n = 32 01 : n = 64 10 : n = 128 11 : not valid 13 reserved r/w 0 reserved 12:0 papcd_thresh r/w 0xfff the threshold for the pap cd trigger.
89 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.37 dac spi configuration register (address = 0x2f) [reset = 0x0000] figure 88. dac spi constant 1 register (spidac_test1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 78. spidac_test1 field descriptions bit field type reset description 15 titest_skipjesd r/w 0 bypasses the jesd logic 14:1 reserved r/w 0x0000 reserved 0 spidac_ena r/w 0 when asserted the dac output is set to the value in register spidac. this can be used for trim setting and other static tests. 8.5.38 dac spi constant register (address = 0x30) [reset = 0x0000] figure 89. dac spi constant register (spidac_test2) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 79. spidac_test2 field descriptions bit field type reset description 15:0 spidac r/w 0x0000 this value replaces the data at the output of the jesd so that the dac value can be controlled
90 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.39 gain for path ab register (address = 0x32) [reset = 0x0000] figure 90. gain for path ab register (gainab) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 80. gainab field descriptions bit field type reset description 15 gainab_ena r/w 0 turns on the path ab gain block 14:12 reserved r/w 0x0 reserved 11:0 gainab r/w 0x400 extra control of gain in the gainab block. this allows a fix gain to be added to the signal if needed. 8.5.40 gain for path cd register (address = 0x33) [reset = 0x0000] figure 91. gain for path cd register (gaincd) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 81. gaincd field descriptions bit field type reset description 15 gaincd_ena r/w 0 turns on the path cd gain block 14:12 reserved r/w 0x0 reserved 11:0 gaincd r/w 0x400 extra control of gain in the gaincd block. this allows a fix gain to be added to the signal if needed.
91 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.41 jesd error counter register (address = 0x41) [reset = 0x0000] figure 92. jesd error counter register (jesd_err_cnt) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r r r r r r r r 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 82. jesd_err_cnt field descriptions bit field type reset description 15:0 jesd_err_cnt r 0x0000 this is the error count for the jesd link. this is a 16bit value that is not cleared until the jesd synchronization is required or errcnt_clr is programmed to '1' 8.5.42 jesd id 1 register (address = 0x46) [reset = 0x0044] figure 93. jesd id 1 register (jesd_id1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r r r r r r r r 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 0 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 83. jesd_id1 field descriptions bit field type reset description 15:11 lid0 r/w 00000 jesd id for lane 0 10:6 lid1 r/w 00001 jesd id for lane 1 5:1 lid2 r/w 00010 jesd id for lane 2 0 reserved r/w 0 reserved
92 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.43 jesd id 2 register (address = 0x47) [reset = 0x190a] figure 94. jesd id 2 register (jesd_id2) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 1 r r r r r r r r legend: r/w = read/write; r = read only; -n = value after reset table 84. jesd id 2 register (jesd_id2) bit field type reset description 15:11 lid3 r/w 00011 jesd id for lane 3 10:6 lid4 r/w 00100 jesd id for lane 4 5:1 lid5 r/w 00101 jesd id for lane 5 0 reserved r/w 0 reserved 8.5.44 jesd id 3 and subclass register (address = 0x48) [reset = 0x31c3] figure 95. jesd id 3 register (jesd_id3) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 85. jesd_id3 field descriptions bit field type reset description 15:11 lid6 r/w 00110 jesd id for lane 6 10:6 lid7 r/w 00111 jesd id for lane 7 5:4 reserved r/w 00 reserved 3:1 subclassv r/w 001 selects the jesd subclass supported. note: ? 001 ? is subclass 1 and ? 000 ? is subclass 0 they are the only modes supported; not used for operation but used for configuration. see field min_latency_ena in register jesd_match ( 9.5.46 ) for use in subclass0 0 jesdv r/w 1 selects the version of jesd support(0=a; 1=b) note: jesd 204b is only supported version.
93 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.45 jesd lane enable register (address = 0x4a) [reset = 0x0003] figure 96. jesd lane enable register (jesd_ln_en) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 0 1 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 86. jesd_ln_en field descriptions bit field type reset description 15:8 lane_ena 0x00 turn on each lane as needed. signal is active high. bit 15 : lane7 enable bit 14 : lane6 enable bit 13 : lane5 enable bit 12 : lane4 enable bit 11 : lane3 enable bit 10 : lane2 enable bit 9 : lane1 enable bit 8 : lane0 enable 7:6 jesd_test_seq 00 set to select and verify link layer test sequences. the error for these sequences comes out the lane alarms bit0. 1= a fail and 0 = pass. 00 : test sequence disabled 01 : verify repeating d.21.5 high frequency pattern for random jitter 10 : verify repeating k.28.5 mixed frequency pattern for deterministic jitter 11 : verify repeating ila sequence 5:2 reserved 0x0 reserved 1:0 jesd_phase_mode 11 used to tell the jesd block how many clock phases are being used for lanes. 00 = 1 phase 01 = 2 phases 10 = 4 phases 11 = 8 phases
94 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.46 jesd rbd buffer and frame octets register (address = 0x4b) [reset = 0x1300] figure 97. jesd rbd buffer and frame octets register (jesd_rbd_f) 15 14 13 12 11 10 9 8 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 87. jesd_rbd_f field descriptions bit field type reset description 15:13 reserved r/w 00 reserved 12:8 rbd r/w 10011 this controls the amount of elastic buffers being used in the jesd. larger numbers will mean more latency; but smaller numbers may not hold enough data to capture the input skew. this value must always be mem_k 7:0 f_m1 r/w 0x00 this is the number of octets in the frame - 1 8.5.47 jesd k and l parameters register (address = 0x4c) [reset = 0x1303] figure 98. jesd k and l parameters register (jesd_k_l) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 0 1 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 88. jesd_k_l field descriptions bit field type reset description 15:13 reserved r/w 000 reserved 12:8 k_m1 r/w 10011 the number of frames in a multi-frame - 1. 0 k - 1 < 32 7:5 reserved r/w 0 reserved 4:0 l_m1 r/w 00011 the number of lanes used by the jesd - 1. 0 l -1 < 8
95 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.48 jesd m and s parameters register (address = 0x4d) [reset = 0x0100] figure 99. jesd m and s parameters register (jesd_m_s) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 0 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 89. jesd_m_s field descriptions bit field type reset description 15:8 m_m1 r/w 0x01 the number of streams per frame - 1. 0 m - 1 < 256 7:5 reserved r/w 000 reserved 4:0 s_m1 r/w 00000 the number of samples per stream per frame - 1. 8.5.49 jesd n, hd and scr parameters register (address = 0x4e) [reset = 0x0f4f] figure 100. jesd n, hd and scr parameters register (jesd_n_hd_scr) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 90. jesd_n_hd_scr field descriptions bit field type reset description 15:13 reserved r/w 000 reserved 12:8 nprime_m1 r/w 01111 the number of adjusted bits per sample - 1 7 reserved r/w 0 reserved 6 hd r/w 1 high density mode. samples can cross the lane boundary 5 scr r/w 0 turn on the scrambler 4:0 n_m1 r/w 01111 the number of bits per sample - 1
96 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.50 jesd character match and other register (address = 0x4f) [reset = 0x1cc1] figure 101. jesd character match and other parameters register (jesd_match) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 91. jesd_match field descriptions bit field type reset description 15:8 match_data r/w 0x1c the character to match for buffer release. normally it is a /r/=/k28.0/-0x1c but with these bits the user can program the value. 7 match_specific r/w 1 match a specific charater to start the jesd buffering when asserted; otherwise the first non-k will start the buffering. 6 match_ctrl r/w 1 when asserted the match character is a control character instead of a data character. 5 no_lane_sync r/w 0 assert if the tx side does not support lane initialization. this way the rx won ? t flag errors in the configuration portion of the ila. 4:2 not used r/w 000 not used 1 min_latency_ena r/w 0 enable minimum latency when set. this is needed for subclass 0 support. 0 jesd_commaalign_ena r/w 1 when asserted the jesd block serdes comma align signal will be added with the serdes align bit(0) to control when to shut off comma alignment. when this bit is deasserted; then the programmed bit(spi_config62(11)) is the only control.
97 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.51 jesd link configuration data register (address = 0x50) [reset = 0x0000] figure 102. jesd link configuration data register (jesd_link_cfg) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 92. jesd_link_cfg field descriptions bit field type reset description 15-12 adjcnt r/w 0x0 lane configuration data for link. reserved by dac38rf8x except for lane configuration checking. 11 adjdir r/w 0 lane configuration data for link. reserved by dac38rf8x except for lane configuration checking. 10-7 bid r/w 0x0 lane configuration data for link. reserved by dac38rf8x except for lane configuration checking. 6-2 cf r/w 00000 lane configuration data for link. reserved by dac38rf8x except for lane configuration checking. 1-0 cs r/w 00 lane configuration data for link. reserved by dac38rf8x except for lane configuration checking. 8.5.52 jesd sync request register (address = 0x51) [reset = 0x00ff] figure 103. jesd sync request register (jesd_sync_req) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 93. jesd_sync_req field descriptions bit field type reset description 15:8 did r/w 0x00 lane configuration 7:0 sync_request r/w 0xff these bits select which errors cause a sync request. sync requests take priority over the error notification; so if sync request isn ? t desired; set these bits to a ? 0 ? . bit 7 = multi-frame alignment error bit 6 = frame alignment error bit 5 = link configuration error bit 4 = elastic buffer overflow (bad rbd value) bit 3 = elastic buffer end char mismatch (match_ctrl match_data) bit 2 = code synchronization error bit 1 = 8b/10b not-in-table code error bit 0 = 8b/10b disparity error
98 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.53 jesd error output register (address = 0x52) [reset = 0x00ff] figure 104. jesd error output register (jesd_err_out) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 94. jesd_err_out field descriptions bit field type reset description 15:10 reserved r/w 000000 reserved 9 disable_err_rpt r/w 0 assertion means that errors will not be reported on the sync_n output. 8 phadj r/w 0 lane configuration 7:0 err_ena r/w 0xff these bits select the errors generated are counted in the err_c for the link. the bits also control what signals are sent out the pad_syncb pin for error notification. bit 7 = multi-frame alignment error bit 6 = frame alignment error bit 5 = link configuration error bit 4 = elastic buffer overflow (bad rbd value) bit 3 = elastic buffer end char mismatch (match_ctrl match_data) bit 2 = code synchronization error bit 1 = 8b/10b not-in-table code error bit 0 = 8b/10b disparity error 8.5.54 jesd ila check 1 register (address = 0x53) [reset = 0x0100] figure 105. jesd ila check 1 register (jesd_ila_cfg1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 95. jesd_ila_cfg1 field descriptions bit field type reset description 15:8 ila_m r/w 0x01 jesd m-1 configuration value used only for ila checking; may be set independently of the actual jesd mode 7:0 ila_f r/w 0x00 jesd f-1 configuration value used only for ila checking; may be set independently of the actual jesd mode
99 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.55 jesd ila check 2 register (address = 0x54) [reset = 0x8e60] figure 106. jesd ila check 2 register (jesd_ila_cfg2) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 96. jesd_ila_cfg2 field descriptions bit field type reset description 15 ila_hd r/w 1 jesd hd configuration value used only for ila checking; may be set independently of the actual jesd mode 14:10 ila_l r/w 00011 jesd l-1 configuration value used only for ila checking; may be set independently of the actual jesd mode 9:5 ila_k r/w 10011 jesd k-1 configuration value used only for ila checking; may be set independently of the actual jesd mode 4:0 ila_s r/w 00000 jesd s-1 configuration value used only for ila checking; may be set independently of the actual jesd mode 8.5.56 jesd sysref mode register (address = 0x5c) [reset = 0x0001] figure 107. jesd sysref mode register (jesd_sysr_mode) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 1 1 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 97. jesd_sysr_mode field descriptions bit field type reset description 15:4 reserved r/w 0x000 reserved 3 err_cnt_clr r/w 0 a transition from 0- > 1 causes the error_cnt to be cleared 2:0 sysref_mode r/w 001 determines how sysref is used in the jesd synchronizing block. 000 = don ? t use sysref pulse 001 = use all sysref pulses 010 = use only the next sysref pulse 011 = skip one sysref pulse then use only the next one 100 = skip one sysref pulse then use all pulses. 101 = skip two sysrefs and then use one 110 = skip two sysrefs and then use all
100 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.57 jesd crossbar configuration 1 register (address = 0x5f) [reset = 0x0123] figure 108. jesd crossbar configuration 1 register (jesd_crossbar1) 15 14 13 12 11 10 9 8 reserved 0 0 0 reserved 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 98. jesd_crossbar1 field descriptions bit field type reset description 15 reserved r/w 0 reserved 14:12 octetpath0_sel r/w 000 these bits are used by the cross-bar switch to map any lane to any other lane. the 3 bit term tells the mapper block what lane this particular lane is supposed to be treated as. 000 = treat as lane0 001 = treat as lane1 010 = treat as lane2 011 = treat as lane3 100 = treat as lane4 101 = treat as lane5 110 = treat as lane6 111 = treat as lane7 11 reserved r/w 0 reserved 10:8 octetpath1_sel r/w 001 these bits are used by the cross-bar switch to map any lane to any other lane. the 3 bit term tells the mapper block what lane this particular lane is supposed to be treated as. 000 = treat as lane0 001 = treat as lane1 010 = treat as lane2 011 = treat as lane3 100 = treat as lane4 101 = treat as lane5 110 = treat as lane6 111 = treat as lane7 7 reserved r/w 0 reserved 6:4 octetpath2_sel r/w 010 these bits are used by the cross-bar switch to map any lane to any other lane. the 3 bit term tells the mapper block what lane this particular lane is supposed to be treated as. 000 = treat as lane0 001 = treat as lane1 010 = treat as lane2 011 = treat as lane3 100 = treat as lane4 101 = treat as lane5 110 = treat as lane6 111 = treat as lane7 3 reserved r/w 0 reserved 2:0 octetpath3_sel r/w 011 these bits are used by the cross-bar switch to map any lane to any other lane. the 3 bit term tells the mapper block what lane this particular lane is supposed to be treated as. 000 = treat as lane0 001 = treat as lane1 010 = treat as lane2 011 = treat as lane3 100 = treat as lane4 101 = treat as lane5 110 = treat as lane6 111 = treat as lane7
101 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.58 jesd crossbar configuration 2 register (address = 0x60) [reset = 0x4567] figure 109. jesd_crossbar2 field dbits to determine what version of build for the chip.escriptions 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 99. jesd_crossbar2 field descriptions bit field type reset description 15 reserved r/w 0 reserved 14:12 octetpath4_sel r/w 100 these bits are used by the cross-bar switch to map any lane to any other lane. the 3 bit term tells the mapper block what lane this particular lane is supposed to be treated as. 000 = treat as lane0 001 = treat as lane1 010 = treat as lane2 011 = treat as lane3 100 = treat as lane4 101 = treat as lane5 110 = treat as lane6 111 = treat as lane7 11 reserved r/w 0 reserved 10:8 octetpath5_sel r/w 101 these bits are used by the cross-bar switch to map any lane to any other lane. the 3 bit term tells the mapper block what lane this particular lane is supposed to be treated as. 000 = treat as lane0 001 = treat as lane1 010 = treat as lane2 011 = treat as lane3 100 = treat as lane4 101 = treat as lane5 110 = treat as lane6 111 = treat as lane7 7 reserved r/w 0 reserved 6:4 octetpath6_sel r/w 110 these bits are used by the cross-bar switch to map any lane to any other lane. the 3 bit term tells the mapper block what lane this particular lane is supposed to be treated as. 000 = treat as lane0 001 = treat as lane1 010 = treat as lane2 011 = treat as lane3 100 = treat as lane4 101 = treat as lane5 110 = treat as lane6 111 = treat as lane7 3 reserved r/w 0 reserved 2:0 octetpath7_sel r/w 111 these bits are used by the cross-bar switch to map any lane to any other lane. the 3 bit term tells the mapper block what lane this particular lane is supposed to be treated as. 000 = treat as lane0 001 = treat as lane1 010 = treat as lane2 011 = treat as lane3 100 = treat as lane4 101 = treat as lane5 110 = treat as lane6 111 = treat as lane7
102 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.59 jesd alarms for lane 0 register (address = 0x64) [reset = 0x0000] figure 110. jesd alarms for lane 0 register (jbits to determine what version of build for the chip.esd_alm_l0) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 0 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 100. jesd_alm_l0 field descriptions bit field type reset description 15:8 alm_lane0_err w0c 0x00 lane0 errors: bit 15 = multiframe alignment error bit 14 = frame alignment error bit 13 = link configuration error bit 12 = elastic buffer overflow (bad rbd value) bit 11 = elastic buffer match error. the first non-/k/ doesn ? t match ? match_ctrl ? and ? match_data ? programmed values. bit 10 = code synchronization error bit 9 = 8b/10b not-in-table code error bit 8 = 8b/10b disparity error 7:4 reserved w0c 0x0 reserved 3:0 alm_fifo0_flags w0c 0x0 lane0 fifo errors: bit 3 = write_error : high if write request and fifo is full (note: only released when jesd block is initialize with mem_init_state) bit 2 = write_full : fifo is full bit 1 = read_error : high if read request with empty fifo (note: only released when jesd block is initialize with mem_init_state) bit 0 = read_empty : fifo is empty
103 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.60 jesd alarms for lane 1 register (address = 0x65 01100101) [reset = 0x0000] figure 111. jesd alarms for lane 1 register (jesd_alm_l1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 1 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 101. jesd_alm_l1 field descriptions bit field type reset description 15:8 alm_lane1_err w0c 0x00 lane1 errors: bit 15 = multiframe alignment error bit 14 = frame alignment error bit 13 = link configuration error bit 12 = elastic buffer overflow (bad rbd value) bit 11 = elastic buffer match error. the first non-/k/ doesn ? t match ? match_ctrl ? and ? match_data ? programmed values. bit 10 = code synchronization error bit 9 = 8b/10b not-in-table code error bit 8 = 8b/10b disparity error 7:4 reserved w0c 0x0 reserved 3:0 alm_fifo1_flags w0c 0x0 lane1 fifo errors: bit 3 = write_error : high if write request and fifo is full (note: only released when jesd block is initialize with mem_init_state) bit 2 = write_full : fifo is full bit 1 = read_error : high if read request with empty fifo (note: only released when jesd block is initialize with mem_init_state) bit 0 = read_empty : fifo is empty
104 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.61 jesd alarms for lane 2 register (address = 0x66) [reset = 0x0000] figure 112. jesd alarms for lane 2 register (jesd_alm_l2) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 0 1 1 0 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 102. jesd_alm_l2 field descriptions bit field type reset description 15:8 alm_lane2_err w0c 0x00 lane2 errors: bit 15 = multiframe alignment error bit 14 = frame alignment error bit 13 = link configuration error bit 12 = elastic buffer overflow (bad rbd value) bit 11 = elastic buffer match error. the first non-/k/ doesn ? t match ? match_ctrl ? and ? match_data ? programmed values. bit 10 = code synchronization error bit 9 = 8b/10b not-in-table code error bit 8 = 8b/10b disparity error 7:4 reserved w0c 0x0 reserved 3:0 alm_fifo2_flags w0c 0x0 lane2 fifo errors: bit 3 = write_error : high if write request and fifo is full (note: only released when jesd block is initialize with mem_init_state) bit 2 = write_full : fifo is full bit 1 = read_error : high if read request with empty fifo (note: only released when jesd block is initialize with mem_init_state) bit 0 = read_empty : fifo is empty
105 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.62 jesd alarms for lane 3 register (address = 0x67) [reset = 0x0000] figure 113. jesd alarms for lane 3 register (jesd_alm_l3) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 0 1 1 1 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 103. jesd_alm_l3 field descriptions bit field type reset description 15:8 alm_lane3_err w0c 0x00 lane3 errors: bit 15 = multiframe alignment error bit 14 = frame alignment error bit 13 = link configuration error bit 12 = elastic buffer overflow (bad rbd value) bit 11 = elastic buffer match error. the first non-/k/ doesn ? t match ? match_ctrl ? and ? match_data ? programmed values. bit 10 = code synchronization error bit 9 = 8b/10b not-in-table code error bit 8 = 8b/10b disparity error 7:4 reserved w0c 0x0 reserved 3:0 alm_fifo3_flags w0c 0x0 lane3 fifo errors: bit 3 = write_error : high if write request and fifo is full (note: only released when jesd block is initialize with mem_init_state) bit 2 = write_full : fifo is full bit 1 = read_error : high if read request with empty fifo (note: only released when jesd block is initialize with mem_init_state) bit 0 = read_empty : fifo is empty
106 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.63 jesd alarms for lane 4 register (address = 0x68) [reset = 0x0000] figure 114. jesd alarms for lane 4 register (jesd_alm_l4) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 1 0 0 0 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 104. jesd_alm_l4 field descriptions bit field type reset description 15:8 alm_lane4_err w0c 0x00 lane4 errors: bit 15 = multiframe alignment error bit 14 = frame alignment error bit 13 = link configuration error bit 12 = elastic buffer overflow (bad rbd value) bit 11 = elastic buffer match error. the first non-/k/ doesn ? t match ? match_ctrl ? and ? match_data ? programmed values. bit 10 = code synchronization error bit 9 = 8b/10b not-in-table code error bit 8 = 8b/10b disparity error 7:4 reserved w0c 0x0 reserved 3:0 alm_fifo4_flags w0c 0x0 lane4 fifo errors: bit 3 = write_error : high if write request and fifo is full (note: only released when jesd block is initialize with mem_init_state) bit 2 = write_full : fifo is full bit 1 = read_error : high if read request with empty fifo (note: only released when jesd block is initialize with mem_init_state) bit 0 = read_empty : fifo is empty
107 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.64 jesd alarms for lane 5 register (address = 0x69) [reset = 0x0000] figure 115. 8.4.60 jesd alarms for lane 5 register (address = 0x69) [reset = 0x0000] 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 1 0 0 1 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 105. jesd_alm_l5 field descriptions bit field type reset description 15:8 alm_lane5_err w0c 0x00 lane5 errors: bit 15 = multiframe alignment error bit 14 = frame alignment error bit 13 = link configuration error bit 12 = elastic buffer overflow (bad rbd value) bit 11 = elastic buffer match error. the first non-/k/ doesn ? t match ? match_ctrl ? and ? match_data ? programmed values. bit 10 = code synchronization error bit 9 = 8b/10b not-in-table code error bit 8 = 8b/10b disparity error 7:4 reserved w0c 0x0 reserved 3:0 alm_fifo5_flags w0c 0x0 lane5 fifo errors: bit 3 = write_error : high if write request and fifo is full (note: only released when jesd block is initialize with mem_init_state) bit 2 = write_full : fifo is full bit 1 = read_error : high if read request with empty fifo (note: only released when jesd block is initialize with mem_init_state) bit 0 = read_empty : fifo is empty
108 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.65 jesd alarms for lane 6 register (address = 0x6a [reset = 0x0000] figure 116. jesd alarms for lane 6 register (jesd_alm_l6) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 1 0 1 0 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 106. jesd_alm_l6 field descriptions bit field type reset description 15:8 alm_lane6_err w0c 0x00 lane6 errors: bit 15 = multiframe alignment error bit 14 = frame alignment error bit 13 = link configuration error bit 12 = elastic buffer overflow (bad rbd value) bit 11 = elastic buffer match error. the first non-/k/ doesn ? t match ? match_ctrl ? and ? match_data ? programmed values. bit 10 = code synchronization error bit 9 = 8b/10b not-in-table code error bit 8 = 8b/10b disparity error 7:4 reserved w0c 0x0 reserved 3:0 alm_fifo6_flags w0c 0x0 lane6 fifo errors: bit 3 = write_error : high if write request and fifo is full (note: only released when jesd block is initialize with mem_init_state) bit 2 = write_full : fifo is full bit 1 = read_error : high if read request with empty fifo (note: only released when jesd block is initialize with mem_init_state) bit 0 = read_empty : fifo is empty
109 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.66 jesd alarms for lane 7 register (address = 0x6b) [reset = 0x0000] figure 117. jesd alarms for lane 7 register (jesd_alm_l7) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 1 0 1 1 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 107. jesd alarms for lane 7 register (jesd_alm_l7) bit field type reset description 15:8 alm_lane7_err w0c 0x00 lane7 errors: bit 15 = multiframe alignment error bit 14 = frame alignment error bit 13 = link configuration error bit 12 = elastic buffer overflow (bad rbd value) bit 11 = elastic buffer match error. the first non-/k/ doesn ? t match ? match_ctrl ? and ? match_data ? programmed values. bit 10 = code synchronization error bit 9 = 8b/10b not-in-table code error bit 8 = 8b/10b disparity error 7:4 reserved w0c 0x0 reserved 3:0 alm_fifo7_flags w0c 0x0 lane7 fifo errors: bit 3 = write_error : high if write request and fifo is full (note: only released when jesd block is initialize with mem_init_state) bit 2 = write_full : fifo is full bit 1 = read_error : high if read request with empty fifo (note: only released when jesd block is initialize with mem_init_state) bit 0 = read_empty : fifo is empty 8.5.67 sysref and pap alarms register (address = 0x6c) [reset = 0x0000] figure 118. sysref and pap alarms register (alm_sysref_pap) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 108. alm_sysref_pap field descriptions bit field type reset description 15:13 reserved w0c 0 reserved 12 alm_sysref_err w0c alarm caused when the sysref is placed at an incorrect location 11 alm_from_shorttest w0c this is the alarm from jesd during the short test checking. 10:7 alm_pap w0c 0x0 the alarms from the pap blocks indicated which pap was triggered. bit0 = papa bit1 = papb bit2 = papc bit3 = papd 6:2 reserved w0c 0x0 reserved 1 alm_div192_zero w0c 0 this is asserted if the clkdiv192 in the cdrv_ser shift register is all zeros. 0 not used w0c 0 not used
110 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.68 clock divider alarms 1 register (address = 0x6d) [reset = 0x0000] figure 119. clock divider alarms 1 register (alm_clkdiv1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x w0c w0c w0c w0c w0c w0c w0c w0c 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 w0c w0c w0c w0c w0c w0c w0c w0c legend: r/w = read/write; r = read only; w0c = write 0 to clear bit; -n = value after reset; -n = value after reset table 109. alm_clkdiv1 field descriptions bit field type reset description 15 alm_div8_zero w0c 0 asserted if the clkdiv8 in the cdrv_ser shift register is all zeros. 14 alm_div12_zero w0c 0 asserted if the clkdiv12 in the cdrv_ser shift register is all zeros. 13 alm_div16_zero w0c 0 asserted if the clkdiv16 in the cdrv_ser shift register is all zeros. 12 alm_div24_zero w0c 0 asserted if the clkdiv24 in the cdrv_ser shift register is all zeros. (connected to the div18 port) 11 alm_div20_zero w0c 0 asserted if the clkdiv20 in the cdrv_ser shift register is all zeros. 10 alm_div32_zero w0c 0 asserted if the clkdiv32 in the cdrv_ser shift register is all zeros. 9 alm_div36_zero w0c 0 asserted if the clkdiv36 in the cdrv_ser shift register is all zeros. 8 alm_div40_zero w0c 0 asserted if the clkdiv40 in the cdrv_ser shift register is all zeros. 7 alm_div48_zero w0c 0 asserted if the clkdiv48 in the cdrv_ser shift register is all zeros. 6 alm_div64_zero w0c 0 asserted if the clkdiv64 in the cdrv_ser shift register is all zeros. 5 alm_div72_zero w0c 0 asserted if the clkdiv72 in the cdrv_ser shift register is all zeros. 4 alm_div80_zero w0c 0 asserted if the clkdiv80 in the cdrv_ser shift register is all zeros. 3 alm_div96_zero w0c 0 asserted if the clkdiv96 in the cdrv_ser shift register is all zeros. 2 alm_div128_zero w0c 0 asserted if the clkdiv128 in the cdrv_ser shift register is all zeros. 1 alm_div144_zero w0c 0 asserted if the clkdiv144 in the cdrv_ser shift register is all zeros. 0 alm_div160_zero w0c 0 asserted if the clkdiv160 in the cdrv_ser shift register is all zeros.
111 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.69 clock configuration register (address = 0x0a) [reset = 0xf000] figure 120. clock configuration register (clk_config) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 110. clk_config field descriptions bit field type reset description 15 rclk_sync_ena rw 1 when asserted the sysref is used to sync the clock divider in the centralclkdiv. this should be disabled after initial syncing. 14 frclk_div_ena rw 1 when asserted the full rate clock divider that provides the div4 phases to the dacs is enabled 13 daca_frclk_ena rw 1 when asserted the full rate clock to the daca block is enabled 12 dacb_frclk_ena rw 1 when asserted the full rate clock to the dacb block is enabled 11 daca_dumdata rw 0 enables dummy data generation for daca when set high 10 dacb_dumdata rw 0 enables dummy data generation for dacb when set high 9:2 reserved rw 0x000 reserved 1 qrclock_daca_ena rw 1 turns on the quarter rate clock for daca when '1' 0 qrclock_dacb_ena rw 1 turns on the quarter rate clock for dacb when '1' 8.5.70 sleep configuration register (address = 0x0b) [reset = 0x0022] figure 121. clock configuration register (sleep_config) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 111. sleep_config field descriptions bit field type reset description 15:9 reserved rw 0000000 reserved 8 vbgr_sleep rw 0 turns off the 'bandgap-over-r' bias 7 reserved rw 0 reserved 6 tsense_sleep rw 0 turns off the temperature sensor 5 pll_sleep rw 1 puts the pll into sleep mode (fuse controlled) 4 clkrecv_sleep rw 0 when asserted the clock input receiver gets put into sleep mode. this also affects the fifo_ostr receiver as well. 3 daca_sleep rw 0 puts the daca into sleep mode 2 dacb_sleep rw 0 puts the dacb into sleep mode 1 clk_tx_sleep rw 1 when asserted the pll tx clock output is in low power mode. 0 reserved rw 0 reserved
112 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.71 divided output clock configuration register (address = 0x0c) [reset = 0x8000] figure 122. divided output clock configuration register (clk_out) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 112. clk_out field descriptions bit field type reset description 15 clk_tx_idle r/w 1 when high puts the clk_tx circuitry in idle mode during which the clktx+ and clktx- output pins are driven to the proper common-mode levels in order to charge the external ac coupling caps. when low allows the divided clock to be driven onto the clktx+ and clktx- output pins. 14:13 clk_tx_divselect r/w 01 selects either div2, div3 or div 4 output. 00 = divided by 3 01 = divided by 4 10 = divided by 2 11 = not valid 12 reserved r/w 0 reserved 11:8 clk_tx_swing r/w 0x0 sets desired swing on clktx+ and clktx- outputs in mvpp- diff 0x0 125 0x1 232 0x2 337 0x3 440 0x4 540 0x5 639 0x6 736 0x7 831 0x8 924 0x9 1012 0xa 1097 0xb 1178 0xc 1255 0xd 1329 0xe 1398 0xf 1462 7:3 reserved r/w 00000 reserved 2 clk_tx_flip r/w 0 flips the polarity of clktx 1 tx_sync_ena r/w 1 syncs the clktx with sysref when asserted 0 extref_ena r/w 0 allows the chip to use an external refernce(1) or the internal reference(0)
113 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.72 dac fullscale current register (address = 0x0d) [reset = 0xf000] figure 123. dac fullscale current register (dacfs) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 113. dacfs field descriptions bit field type reset description 15:12 dacfs r/w 0xf scales the output current is 16 equal steps from 10-40ma (10ma + 2ma*dacfs) 10:0 reserved r/w 0x000 reserved 8.5.73 internal sysref generator register (address = 0x10) [reset = 0x0000] figure 124. internal sysref register (lcmgen) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 114. lcmgen field descriptions bit field type reset description 15:4 reserved r/w 0x00 reserved 3 lcmgen_ena r/w 0 enables the lcm custom logic 2 lcmgen_reset r/w 0 reset the lcm custom logic 1 lcmgen_spi_sysref_ena r/w 0 tbd 0 lcm_sysref_outsel r/w 0 chooses between internal and external sysref 8.5.74 counter for internal sysref generator register (address = 0x11) [reset = 0x0000] figure 125. counter for internal sysref generator register (lcmgen_div) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 115. lcmgen_div field descriptions bit field type reset description 15:0 lcmgen_div r/w 0x00 counter setting for the lcmgen block
114 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.75 spi sysref for internal sysref generator register (address = 0x12) [reset = 0x0000] figure 126. spi sysref for internal sysref generator register (lcmgen_spisysref) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 116. lcmgen_spisysref field descriptions bit field type reset description 15:1 reserved r/w 0x00 reserved 0 lcmgen_spi_sysref r/w 0 spi sysref for the lcmgen block 8.5.76 digital test signals register (address = 0x1b) [reset = 0x0000] figure 127. digital test signals register (dtest) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 1 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 117. dtest field descriptions bit field type reset description 15 reserved r/w 0 reserved 14:12 dtest_lane r/w 000 selects the lane to check for the signals selected by field dtest 11:8 dtest r/w 0x0 allows digital test signals to come out the alarm pin. 0000 : test disabled; normal alarm pin function 0001 : serdes lanes 0 ? 3 pll clock/80 0010 : serdes lanes 4 ? 7 pll clock/80 0011 : testfail (lane selected by field dtest_lane) 0100 : sync (lane selected by field dtest_lane) 0101 : ocip (lane selected by field dtest_lane) 0110 : equnder (lane selected by field dtest_lane) 0111 : eqover (lane selected by field dtest_lane) 1000 ? 1111 : not used 7:0 reserved r/w 0x00 reserved
115 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.77 sleep pin control register (address = 0x23) [reset = 0xffff] these fields control the routing of the sleep signal to different blocks. assertion means that the sleep signal will be sent to the block. these bits do not override the spi bits; just the sleep signal from the pad. figure 128. sleep pin control register (sleep_cntl) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 118. sleep_cntl field descriptions bit field type reset description 15:10 reserved r/w 11111 reserved 9 clkout_sleep r/w 1 allows the output clock to sleep 8 bg_sleep r/w 1 allows the band gap to sleep 7 temp_sleep r/w 1 allows the temp sensor to sleep 6 pll_cp_sleep r/w 1 allows the pll charge pump to sleep 5 pll_sleep r/w 1 allows the pll to sleep 4 clk_recv_sleep r/w 1 allows the clock receiver to sleep 3:2 reserved r/w 11 reserved 1 dacb_sleep r/w 1 allows dacb to sleep 0 daca_sleep r/w 1 allows daca to sleep
116 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.78 sysref capture circuit control register (address = 0x24) [reset = 0x1000] figure 129. sysref capture circuit control register (sysr_capture) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 119. sysr_capture field descriptions bit field type reset description 15:14 sysr_phase_wdw r/w 00 sysref phase alignment tolerance window centers sysref capture window as follows: 00 = centered on phase 12 (**default**) 01 = centered on phase 23 10 = centered on phase 34 11 = centered on phase 41 13:12 sysr_align_dly r/w 01 sysref alignment offset delay optional alignment offset that allows system designer to work around hardware (e.g. pcb) alignment errors by letting him specify that the sysref pulse should be treated as occurring one device clock earlier or later than its observed position. legal settings are as follows: 00 = offset by -1 device clock cycles. treat sysref as if it were captured 1 cycle earlier. 01 = no offset (**default**) 10 = offset by +1 device clock cycles. treat sysref as if it were captured 1 cycle later. 11 = reserved 11 sysr_status_ena r/w 0 enable alignment status monitoring enable logic that generates sysref alignment status information and accumulates statistics that can be read by the user. 0 = disable sysref alignment status outputs (**default**). used during normal operation. 1 = enable sysref alignment status outputs. used when characterizing sysref capture timing. 10:2 reserved r/w 0x000 reserved 1 sysr_align_sync r/w 0 write a ? 1 ? to this bit to clear accumulated sysref align statistics 0 sysr_byps_align r/w 0 bypass sysref alignment logic. bypass the 4x oversampled sysref alignment logic and instead capture the sysref signal using the legacy implementation of a flip-flop clocked directly by the rising edge of the device clock. 0 = capture sysref using full-featured alignment circuit (**default**) 1 = bypass sysref alignment logic note: when mem_sysref_bypass_align is enabled, the other sysref alignment controls have no effect.
117 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.79 clock input and pll configuration register (address = 0x31) [reset = 0x0200] figure 130. clock input and pll configuration register (clk_pll_cfg) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 120. clock input and pll configuration register (clk_pll_cfg) bit field type reset description 15:14 reserved r/w 00 reserved 13 sel_extclk_diffse r/w 0 selects the external differential or single ended clock for dacclk. 0 = differential 1 = single ended 12 pll_reset r/w 0 when set the m divider; n divider and pfd are held reset 11 pll_ndivsync_ena r/w 0 when asserted; the sysref input is used to sync the n dividers of the pll. 10 pll_ena r/w 0 enables the pll output as the dac clock when set; the clock provided at the dacclkp/n is used as the pll reference clock. when cleared; the pll is bypassed and the clock provided at the dacclkp/n pins is used as the dac clock 9 pll_cp_sleep r/w 1 must be set to '0' for proper pll operation. 1 = charge pump is put to sleep and can be driven by external source through the atest pins. 8 reserved r/w 0 reserved 7:3 pll_n_m1 r/w 00000 reference clock divider; divide by is n+1 2:0 lockdet_adj r/w 000 adjusts the lock detector sensitivity. upper bit isn't used: x00 - highest sensitivity x11 - lowest sensitivity
118 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.80 pll configuration 1 register (address = 0x32) [reset = 0x0308] figure 131. pll configuration 1 register (pll_config1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 121. config1 field descriptions bit field type reset description 15:8 pll_m_m1 r/w 0x03 vco feedback divider; divide by is 4(m+1) 7:4 reserved r/w 0x0 reserved 3:0 pll_vco_rdac r/w 0x8 controls the vco amplitude 8.5.81 pll configuration 2 register (address = 0x33) [reset = 0x4018] figure 132. pll configuration 2 register (pll_config2) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 122. pll_config2 field descriptions bit field type reset description 15 pll_vcosel r/w 0 selects between two vcos 0 = 5.9 ghz vco(2 turn inductor in upper vco) 1 = 8.9 ghz vco (1 turn in the lower vco) 14:8 pll_vco r/w 1000000 vco frequency range 7:6 reserved r/w 000 reserved 5:2 pll_cp_adj r/w 0110 adjusts the charge pump current; 0 to 1.55 ma in 50 a steps. setting to 0000 will hold the lpf pin at 0 v 1 reserved r/w 0 reserved 0 gsmpll_ena r/w 0 enables the gsm pll (coupled vcos) if asserted
119 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.82 lvds output configuration register (address = 0x34) [reset = 0x0000] figure 133. lvds output configuration register (lvds_config) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 123. lvds_config field descriptions bit field type reset description 15 lvds_lopwrb r/w 0 lvds output current control lsb; allows output current to be scaled from ~2 ma to ~4 ma 14 lvds_lopwra r/w 0 lvds output current control msb; allows output current to be scaled from ~2 ma to ~4 ma 13 lvds_lpsel r/w 0 sync lvds output on chip termination control; 100 when cleared; 200 output current settings for the combination of bits 15:13 110 = 4.00 ma 010 = 3.50 ma 100 = 3.00 ma 000 = 2.50 ma ? default current 111 = 4.00 ma 011 = 3.33 ma 101 = 2.66 ma 001 = 2.00 ma 12 lvds_efuse_sel r/w 0 enable lvds bias bandgap reference voltage to the atest multiplexer. 11:10 lvds_trim r/w 00 adjusts the lvds 1.2 v reference. lvds_trim_ena must be set and lvds_efuse_sel must be cleared for these bits to have any effect. 10 +70 mv 00 -70 mv 01 default 11 -20 mv. 9 lvds_trim_ena r/w 0 when set and lvds_efuse_sel is cleared; the lvds_trim adjustment is enabled. when cleared; the lvds_trim has no effect. 8 lvds_sync0\_pd r/w 0 the sync0 lvds output is in power down. 7 reserved r/w 0 reserved 6 lvds_sync0\_cm r/w 0 sync0 lvds output common mode is 1.2 v when cleared; 0.9 v when set. 5:0 reserved r/w 0x00 reserved
120 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.83 fuse farm clock divider register (address = 0x35) [reset = 0x0018] figure 134. fuse farm clock divider register (pll_fdiv) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 1 0 1 1 r/w r/w r/1w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after rese1t table 124. pll_fdiv field descriptions bit field type reset description 15 serdes_clk_sel r/w 0 select either the pll output of the dacclk from the pad. 0 = dacclk pad 1 = pll output 14:11 serdes_refclk_div r/w 0x0 the divide amount for the serdes refclk 10:2 reserved r/w 0x000 reserved 1:0 serdes_refclk_prediv r/w 10 these bits select the pre-divide on the dacclk input clock before the dacclk is used in the dividers used in the serdes pll refclk and the fusefarm sysclk. 00 = if dacclk input 2 ghz; prediv is set to div1 01 = if dacclk input is 4 ghz and > 2 ghz, prediv is set to div2 10 = if dacclk input is 9 ghz and > 4 ghz, prediv is set to div4 11 = not valid
121 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.84 serdes clock configuration register (address = 0x3b) [reset = 0x0002] figure 135. serdes clock configuration register (srds_clk_cfg) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 1 0 1 1 r/w r/w r/1w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after rese1t table 125. srds_clk_cfg field descriptions bit field type reset description 15 serdes_clk_sel r/w 0 select either the pll output of the dacclk from the pad. 0 = dacclk pad 1 = pll output 14:11 serdes_refclk_div r/w 0x0 the divide amount for the serdes refclk 10:2 reserved r/w 0x000 reserved 1:0 serdes_refclk_prediv r/w 10 these bits select the pre-divide on the dacclk input clock before the dacclk is used in the dividers used in the serdes pll refclk and the fusefarm sysclk. 00 = if dacclk input 2 ghz; prediv is set to div1 01 = if dacclk input is 4 ghz and > 2 ghz, prediv is set to div2 10 = if dacclk input is 9 ghz and > 4 ghz, prediv is set to div4 11 = not valid 8.5.85 serdes pll configuration register (address = 0x3c) [reset = 0x8228] figure 136. serdes pll configuration register (srds_pll_cfg) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 1 1 0 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 126. srds_pll_cfg field descriptions bit field type reset description 15 endivclk r/w 1 enable divided by 5 output clock 14:3 clkbyp r/w 00 serdes clock bypass 12:11 lb r/w 00 serdes pll loop bandwidth 10 sleeppll r/w 0 serdes pll sleep 9 vrange r/w 1 serdes pll loop filter range 8:1 mpy r/w 00010100 serdes reference clock multiply factor 0 correct r/w 0 and'ed with lane_ena so it must be set to 1 for correct behavior
122 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.86 serdes configuration 1 register (address = 0x3d) [reset = 0x0x0088] figure 137. serdes configuration 1 register (srds_cfg1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 1 1 0 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 127. rds_cfg1 field descriptions bit field type reset description 15 reserved r/w 0 reserved 14:12 testpatt r/w 000 test pattern 11 bsinrxn r/w 0 enable boundary scan - pins 10 bsinrxp r/w 0 enable boundary scan + pins 9:8 loopback r/w 00 enable loopback 7 enoc r/w 1 enable serdes offset compensation 6 eqhld r/w 0 equalizer hold 5:3 eq r/w 001 serdes equalizer 2:0 cdr r/w 000 clock data recovery algorithm settings
123 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.87 serdes configuration 2 register (address = 0x3e) [reset = 0x0x0909] figure 138. serdes configuration 2 register (srds_cfg2) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 0 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 128. srds_cfg2 field descriptions bit field type reset description 15:13 los r/w 000 enables loss of signal detection. 000 - enable detection 100 - disable detection other - reserved 12:11 align r/w 01 enables external or internal symbol alignment 10:8 term r/w 001 valid programming: 001 ? ac coupling with common mode = 0.7 v 100 ? 0 v common mode. 101 ? 0.25 v common mode 111 ? dc coupling with common mode of 0.6 v. (note: this is not compatible with jesd) 7 reserved r/w 0 reserved 6:5 rate r/w 00 selects full, half, quarter or eighth rate operation. 4:2 buswidth r/w 010 selects the parallel interface width (16 or 20 bits) 1 sleeprx r/w 0 powers the receiver down into the sleep (fast power up) state when high. 0 reserved r/w 1 reserved
124 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.5.88 serdes polarity control register (address = 0x3f) [reset = 0x0000] figure 139. serdes polarity control register (srds_pol) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset table 129. srds_pol field descriptions bit field type reset description 15:8 reserved r/w 0x00 reserved 7:0 invpair r/w 0x00 allows the pn pairs of the different lanes to be inverted. bit 7 = lane7 bit 6 = lane6 bit 5 = lane5 bit 4 = lane4 bit 3 = lane3 bit 2 = lane2 bit 1 = lane1 bit 0 = lane0 8.5.89 jesd204b syncb output register (address = 0x76) [reset = 0x0000] figure 140. jesd204b syncb output register (syncbout) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 1 1 1 0 1 1 r/w r/w r/1w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after rese1t table 130. syncbout field descriptions bit field type reset description 15:2 reserved r/w 0x00 reserved 1 syncbout1 r/w 0 if the cmos sync outputs are turned on, this bit will show the status of the jesd syncb1 signal 0 syncbout0 r/w 0 if the cmos sync outputs are turned on, this bit will show the status of the jesd syncb0 signal
125 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information 9.1.1 start-up sequence figure 141. dac38rf8xx recommended startup sequence pull txenable low x provide all 1v supply rails, 1.8v rails and -1.8v rail. x pull trstb pin of the jtag port low x provide a clock to the differential or single ended cl ock input x toggle resetb pin low then high (recommended pulse du ration >10us) read spi page 0, register 0x7f configure the spi resgisters for the desired mode bits[15:10]=10000b on chip pll mode start sysref generation no read page 0, address 0x06 die temp = bits[15:8] lf voltage = bits[7:5] increment/decrement vco tune value spi page 4, address 0x33, bits[14:8] 85c < die temp < 105c, lf voltage =5 40c 126 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.2 typical application: multi-band radio frequency transmitter the dac38rf8xx device family can be used in rf transmitters designed to support multiple operating bands. the two transmit antennae system shown in figure 142 uses dac38rf8xx to convert digital baseband signals from an fpga directly to rf signals in lte downlink band 1 (2110 mhz - 2170 mhz) and band 3 (1805 mhz - 1880 mhz). figure 142. two antennae multi-band radio frequency transmitter 9.2.1 design requirements table 131. dual band lte downlink transmitter parameter value operating bands band 1 (2110 mhz - 2170 mhz) and band 3 (1805 mhz to 1880 mhz) data rate (baseband) 368.64 mhz sampling frequency 8847.36 mhz interpolation 24 jesd204b interface configuration l-m-f-s-hd = 8-8-2-1-0 ch b ch a fpga adc 2:1 band1 and band3 band1 and band3 syncb syncb 4 lanes 4 lanes 8 lanes device clock sysref 2:1 pa 2:1 pa dac38rfxx 50 q 50 q pll copyright ? 2016, texas instruments incorporated
127 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 9.2.2 detailed design procedure two complex data streams of 20mhz lte data generated in a baseband processor (fpga/asic) is formatted based on table 18 and transmitted to dac38rf8xx. inside dac38rf8xx, the complex input data at a rate of 368.64 msps is interpolated 24 times to the final output sampling rate of 8847.36 msps. this enables the final rf output to be positioned in the first nyquist zone for minimal attenuation due to sinc(x) roll off. after interpolation, the output complex data stream is digitally mixed to the final rf frequencies. the digital mixing eliminates system imperfections such as local oscillator (lo) feed-through and sideband images that are inherent in analog mixers. detailed block diagram is shown in ( figure 143 ) to simplify the system clocking, a low frequency clock (or device clock) is provided as a reference to the on-chip pll ( internal pll/vco ) of dac38rf8xx. the pll generates a low phase noise, high frequency sampling clock from the low frequency reference. figure 143. dual band lte downlink transmitter block diagram 9.2.2.1 calculating the jesd204b serdes rate serdes rate = 1.25 x (m/l) x baseband data rate x number of bits per sample (16) m is a jesd204b interface parameter that refers to the number of data streams from fpga to dac l is a jesd204b interface parameter that refers to the number of serdes lanes used to transmit data 1.25 is a factor due to the 8b10b encoding of the baseband data example, if the baseband data rate = 368.64 msps and l-m-f-s-hd = 8-8-2-1-0 serdes rate = 1.25 x (8/8) x 368.64 x 16 = 7.3728 gbps (15) 9.2.2.2 calculating valid jesd204b sysref frequency valid sysref frequencies depend on the following parameters: 1. sample clock frequency 2. jesd204b internal clock divider value ( clkjesd_div ). this depends on the dac jesd204b l-m-f-s mode and interpolation 3. number of octets in a frame (f) 4. number of frames in a multi-frame (k) maximum sysref frequency = (sample clock frequency/n), where n =lcm(clkjesd_div,4 x k x f). n is the least common multiple of 4 x k x f and clkjesd_div . all valid sysref frequencies are integer divisors of the maximum sysref frequency. example: 24x interpolation jesd interface 1.8425 ghz 24x interpolation 2.14 ghz i data q data i data q data 0 -184.32m +184.32m 0 -184.32m +184.32m 1.84g 2.14g 0 fpga serdes interface dac38rf8xx rf output fs/2
128 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated given sampling clock frequency = 8.84736 gsps, interpolation = 24, dac mode=l-m-f-s=8-8-2-1 and k=20: clkjesd_div = 24 ( clkjesd_div ) maximum sysref frequency = 8847.36 mhz/240 = 36.864 mhz valid sysref frequencies = 36.864 mhz/n, where n is any positive integer. 9.2.3 application curves figure 144. dual band acpr performance in downlink band 3 with on-chip pll
129 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 145. dual band acpr performance in downlink band 1 with on-chip pll
130 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 10 power supply recommendations internally, dac38rfxx comprises a digital subsystem, an analog subsystem, and a clock subsystem. ideally, the power supply scheme should be partitioned according to these three relatively independent blocks to minimize interactions between them. most importantly, sensitive analog and clock circuit power supply must be separated from digital switching noise to reduce direct coupling and mixing of switching spurs. table 132 shows the power supply rails for dac38rfxx grouped under their respective domains. table 132. power supply domains supply rail nominal voltage (v) domain vddig1 +1.0 digital vddio18 +1.8 vddr18 +1.8 vdds18 +1.8 vddt1 +1.0 vdde1 +1.0 vddl1_1 +1.0 vee18n -1.8 analog vdda1 +1.0 vdda18 +1.8 vddout18 +1.8 vddpll1 +1.0 clock vddapll18 +1.8 vddavco18 +1.8 vddclk1 +1.0 vddl2_1 +1.0 vddtx1 +1.0 vddtx18 +1.8 an example power supply scheme suitable for most applications of dac38rfxx is shown in figure 146 . it is recommended to use ferrite beads (fb) to isolate the individual rails from each other. figure 146. power supply scheme for dac38rfxx
131 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.1 power supply sequencing there are no power supply sequencing requirements for all the 1-v and 1.8-v power supplies. for the -1.8 v vee18 rail, it is recommended that this supply is the last to be enabled. enabling vee18 (while other supply voltages are disabled) can cause a small negative voltage to be present at the other rails (that is, vdda1 and vdddig1). this small negative voltage can interfere with the startup of some dc-dc converters or ldo's connected to the 1 v and 1.8 v input power rails.
132 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 layout 11.1 layout guidelines ? dac rf output traces ? single-ended 50 co-planar wave guide for output traces is recommended. ? use short rf traces. place dac close to edge of pcb to shorten the length of output and clock traces. this helps to minimize pcb loss and coupling ? avoid width/spacing differences when entering a landing pad (eg. a balun) by tapering or by redefining width/space rules for the traces ? power supply planes ? ensure sufficient lateral spacing between two power planes (about 3x the thickness of the plane is recommended) ? insert ground plane between adjacent power planes where possible figure 147. example power plane routing ? bypass capacitors ? use bypass capacitors with in-pad vias and place between the pin and the power plane. avoid sharing ground vias or pads of bypass caps used for different power rails ? minimize stubs on bypass capacitors to avoid parasitic inductance
133 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated layout guidelines (continued) figure 148. bypass capacitors placed on the power supply pin with in-pad vias ? high speed serdes traces ? route all serdes traces straight and minimized sharp curves or serpentines. route for best signal integrity ? some skew between serdes traces can be tolerated. it is recommended to limit skew between traces to 320ps or less ? place ground planes between the serdes traces for improved isolation figure 149. layout example of high speed serdes traces
134 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 slasef4 ? february 2017 www.ti.com product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 11.2 layout example figure 150. layout example of dac38rfxx a b c d e f g h j k l m 12 11 10 9 8 5 4 3 2 1 xx xx xx xx x x x x x x xx xx xx xx xx xx x x x x x x x x x xx xx 7 6 xx xx xx xx xx xx xx x x x xx x x x x xx xx xx x xx xx xx x x xx xx xx xx xx xx x x x xx xx xx x xx xx xx xx xx xx xx xx x x x x xx xx x x xx xx x x x x xx xx x x x x x x xx xx xx xx xx xx x x x x xx xx xx xx xx xx x x x x x x x x x x xx xx x x x x xx xx xx xx xx xx x x x x x x bottom trace top trace capacitor resistor x x via rbias x xx x
135 dac38rf86 , dac38rf87 dac38rf97 , dac38rf96 www.ti.com slasef4 ? february 2017 product folder links: dac38rf86 dac38rf87 dac38rf97 dac38rf96 submit documentation feedback copyright ? 2017, texas instruments incorporated 12 device and documentation support 12.1 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 133. related links parts product folder order now technical documents tools & software support & community dac38rf86 click here click here click here click here click here dac38rf87 click here click here click here click here click here dac38rf96 click here click here click here click here click here dac38rf87 click here click here click here click here click here 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 20-feb-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples dac38rf86iaav preview fcbga aav 144 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 dac38rf86i dac38rf86iaavr preview fcbga aav 144 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 dac38rf86i dac38rf87iaav preview fcbga aav 144 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 dac38rf87i dac38rf87iaavr preview fcbga aav 144 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 dac38rf87i dac38rf96iaav preview fcbga aav 144 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 dac38rf96i dac38rf96iaavr preview fcbga aav 144 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 dac38rf96i DAC38RF97IAAV preview fcbga aav 144 168 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 dac38rf97i DAC38RF97IAAVr preview fcbga aav 144 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 dac38rf97i (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 20-feb-2017 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
www.ti.com package outline c 1.94 max typ 0.405 0.325 8.8 typ 8.8 typ 0.8 typ 0.8 typ 144 x 0.51 0.41 (0.68) a 10.15 9.85 b 10.15 9.85 (0.6) typ ( 8) (0.5) (0.6) typ fcbga - 1.94 mm max height aav0144a ball grid array 4219578/a 04/2016 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. dimension is measured at the maximum solder ball diameter, parallel to primary datum c. 4. primary datum c and seating plane are defined by the spherical crowns of the solder balls. ball a1 corner seating plane ball typ 0.2 c note 4 m l k j h g f e d c b a 1 2 3 0.15 c a b 0.08 c symm symm 4 note 3 5 6 7 8 9 10 11 12 scale 1.400
www.ti.com example board layout 144 x ( ) 0.4 (0.8) typ (0.8) typ ( ) metal 0.4 0.05 max solder mask opening metal under solder mask ( ) solder mask opening 0.4 0.05 min fcbga - 1.94 mm max height aav0144a ball grid array 4219578/a 04/2016 notes: (continued) 5. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number spru811 (www.ti.com/lit/spru811). symm symm land pattern example scale:8x 1 a b c d e f g h j k l m 2 3 4 5 6 7 8 9 10 11 12 non-solder mask defined (preferred) solder mask details not to scale solder mask defined
www.ti.com example stencil design (0.8) typ (0.8) typ 144 x ( ) 0.4 fcbga - 1.94 mm max height aav0144a ball grid array 4219578/a 04/2016 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. solder paste example based on 0.15 mm thick stencil scale:8x symm symm 1 a b c d e f g h j k l m 2 3 4 5 6 7 8 9 10 11 12
important notice for ti design information and resources texas instruments incorporated ( ? ti ? ) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, ? ti resources ? ) are intended to assist designers who are developing applications that incorporate ti products; by downloading, accessing or using any particular ti resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this notice. ti ? s provision of ti resources does not expand or otherwise alter ti ? s applicable published warranties or warranty disclaimers for ti products, and no additional obligations or liabilities arise from ti providing such ti resources. ti reserves the right to make corrections, enhancements, improvements and other changes to its ti resources. you understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications (and of all ti products used in or for your applications) with all applicable regulations, laws and other applicable requirements. you represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. you agree that prior to using or distributing any applications that include ti products, you will thoroughly test such applications and the functionality of such ti products as used in such applications. ti has not conducted any testing other than that specifically described in the published documentation for a particular ti resource. you are authorized to use, copy and modify any individual ti resource only in connection with the development of applications that include the ti product(s) identified in such ti resource. no other license, express or implied, by estoppel or otherwise to any other ti intellectual property right, and no license to any technology or intellectual property right of ti or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti products or services are used. information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. use of ti resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. ti resources are provided ? as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding ti resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify you against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. you agree to fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of your non- compliance with the terms and provisions of this notice. this notice applies to ti resources. additional terms apply to the use and purchase of certain types of materials, ti products and services. these include; without limitation, ti ? s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm ), evaluation modules , and samples ( http://www.ti.com/sc/docs/sampterms.htm ). mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2017, texas instruments incorporated

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